×
验证码:
换一张
Forgotten Password?
Stay signed in
Login With UMPASS
English
|
繁體
Login With UMPASS
Log In
ALL
ORCID
TI
AU
PY
SU
KW
TY
JN
DA
IN
PB
FP
ST
SM
Study Hall
Image search
Paste the image URL
Home
Faculties & Institutes
Scholars
Publications
Subjects
Statistics
News
Search in the results
Faculties & Institutes
INSTITUTE OF MIC... [2]
THE STATE KEY LA... [1]
Faculty of Scien... [1]
Authors
RUI PAULO DA SIL... [1]
MAK PUI IN [1]
CHEN YONG [1]
YU WEI HAN [1]
Document Type
Conference paper [1]
Journal article [1]
Date Issued
2021 [1]
2019 [1]
Language
英語English [2]
Source Publication
2021 IEEE Intern... [1]
IEEE Transaction... [1]
Indexed By
SCIE [1]
Funding Organization
Funding Project
×
Knowledge Map
UM
Start a Submission
Submissions
Unclaimed
Claimed
Attach Fulltext
Bookmarks
Browse/Search Results:
1-2 of 2
Help
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Issue Date Ascending
Issue Date Descending
Title Ascending
Title Descending
Author Ascending
Author Descending
WOS Cited Times Ascending
WOS Cited Times Descending
Submit date Ascending
Submit date Descending
Journal Impact Factor Ascending
Journal Impact Factor Descending
A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects
Conference paper
Ming Zhong, Qingwen Wang, Yong Chen, Jian Liu, Liyuan Liu, Xinghua Wang, Xiaoming Xiong, Nan Qi. A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects[C]:IEEE, 2021, 255-256.
Authors:
Ming Zhong
;
Qingwen Wang
;
Yong Chen
;
Jian Liu
;
Liyuan Liu
; et al.
Favorite
|
TC[Scopus]:
7
|
Submit date:2022/05/13
Clock And Data Recovery (Cdr)
Driver
Equalization
Serializer
Source-series-terminated (Sst)
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS
Journal article
Fan,Chao, Yu,Wei Han, Mak,Pui In, Martins,Rui P.. A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(12), 4850-4861.
Authors:
Fan,Chao
;
Yu,Wei Han
;
Mak,Pui In
;
Martins,Rui P.
Favorite
|
TC[WOS]:
9
TC[Scopus]:
8
IF:
5.2
/
4.5
|
Submit date:2021/03/09
Cmos
Current-mode-logic (Cml) Driver
Feed-forward Equalization (Ffe)
Four-level Pulse-amplitude Modulation (Pam-4)
Source-series-terminated (Sst) Driver
Sst-cml-hybrid (Sch) Driver
Transmitter (Tx)