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Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area Journal article
Wang, Guan Cheng, Zhu, Yan, Chan, Chi-Hang, Seng-Pan, U., Martins, Rui P.. Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26(11), 2279-2289.
Authors:  Wang, Guan Cheng;  Zhu, Yan;  Chan, Chi-Hang;  Seng-Pan, U.;  Martins, Rui P.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:2.8/2.8 | Submit date：2019/01/17
Bridge Digital-to-analog Converter (Dac)  Gain Error Calibration  Successive Approximation Register (Sar)  Analog-to-digital Converters (Adcs)  Testing Signal Generation (Tsg)  
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
Qiu, Lei, Tang, Kai, Zheng, Yuanjin, Siek, Liter, Zhu, Yan, U, Seng-Pan. A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26(3), 572-583.
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan; et al.
Favorite | TC[WOS]:15 TC[Scopus]:16  IF:2.8/2.8 | Submit date：2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew  
High Performance SAR-Type ADCs & Digital Assisted Techniques Book chapter
出自: Power, RF and Mixed-Signal ICs:River Publishers, 2018, 页码:156-182
Authors:  Zhu, Y.
Favorite |  | Submit date：2023/08/31
SAR-Type ADCs  Digital Assisted Techniques  
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration Conference paper
Qiu L., Kai T., Zhu Y., Siek L., Zheng Y., Seng-Pan U.. A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration[C], 2017, 77-80.
Authors:  Qiu L.;  Kai T.;  Zhu Y.;  Siek L.;  Zheng Y.; et al.
Favorite | TC[WOS]:11 TC[Scopus]:10 | Submit date：2019/02/14
Sar Adcs  Time Skew Calibration  Time-interleaved  
Split-SAR ADCs: Improved linearity with power and speed optimization Journal article
Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti. Split-SAR ADCs: Improved linearity with power and speed optimization[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(2), 372-383.
Authors:  Yan Zhu;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:44 TC[Scopus]:56 | Submit date：2018/10/30
Linearity Analysis  Linearity Calibration  Sar Adcs  Split Dac  Vcm-based Switching