This paper presents a 10-bit 1GS/s 4-way time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To reduce the time skew among the TI channels, the master clock based sampling technique is adopted that can effectively suppress the interleaving spurs to -54dB at Nyquist input. Morever, a tap-interpolating fractional delay (TIFD) filters based time skew calibration technique is proposed, which operates at background and can further reduce the interleaving spurs to be less than -70dB. The prototype was fabricated in a 65nm CMOS technology. The measurement results show that the ADC operating at 1GS/s achieves a SNDR of 49.6dB and SFDR of 61.6dB at Nyquist input resulting in a figure of merit (FoM) of 32fJ/conversion-step.