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A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
Zhu Y., Chan C.-H., Zheng Z.-H., Li C., Zhong J.-Y., Martins R.P.. A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(11), 3606-3616.
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.; et al.
Favorite | TC[WOS]:13 TC[Scopus]:14 | Submit date：2019/02/11
Passive Sharing  Pipelined-sar Adc  Sampling Front-end Design  Switch Bootstrap Technique  Time-interleaved Adc  
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Zhu, Yan, Chan, Chi-Hang, Zheng, Zi-Hao, Li, Cheng, Zhong, Jian-Yu, Martins, Rui P.. A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS[C], 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018, 3606-3616.
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu; et al.
Favorite | TC[WOS]:13 TC[Scopus]:14 | Submit date：2018/10/30
Time-interleaved Adc  Sampling Front-end Design  Passive Sharing  Pipelined-sar Adc  Switch Bootstrap Technique