×
验证码:
换一张
Forgotten Password?
Stay signed in
Login With UMPASS
English
|
繁體
Login With UMPASS
Log In
ALL
ORCID
TI
AU
PY
SU
KW
TY
JN
DA
IN
PB
FP
ST
SM
Study Hall
Image search
Paste the image URL
Home
Faculties & Institutes
Scholars
Publications
Subjects
Statistics
News
Search in the results
Faculties & Institutes
THE STATE KEY LA... [5]
INSTITUTE OF MIC... [5]
Faculty of Scien... [5]
Authors
RUI PAULO DA SIL... [5]
MAK PUI IN [5]
CHEN YONG [4]
YIN JUN [1]
Document Type
Journal article [3]
Conference paper [2]
Date Issued
2023 [2]
2022 [2]
2021 [1]
Language
英語English [5]
Source Publication
Analog Integrate... [1]
ICECS 2022 - 29t... [1]
IEEE MTT-S Inter... [1]
IEEE Transaction... [1]
International Jo... [1]
Indexed By
SCIE [3]
CPCI-S [2]
Funding Organization
Funding Project
×
Knowledge Map
UM
Start a Submission
Submissions
Unclaimed
Claimed
Attach Fulltext
Bookmarks
Browse/Search Results:
1-5 of 5
Help
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Issue Date Ascending
Issue Date Descending
Title Ascending
Title Descending
Author Ascending
Author Descending
WOS Cited Times Ascending
WOS Cited Times Descending
Submit date Ascending
Submit date Descending
Journal Impact Factor Ascending
Journal Impact Factor Descending
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique
Journal article
Wang,Lin, Chen,Yong, Yang,Chaowei, Zhao,Xiaoteng, Mak,Pui In, Maloberti,Franco, Martins,Rui P.. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(7), 2637-2650.
Authors:
Wang,Lin
;
Chen,Yong
;
Yang,Chaowei
;
Zhao,Xiaoteng
;
Mak,Pui In
; et al.
Favorite
|
TC[WOS]:
1
TC[Scopus]:
4
IF:
5.2
/
4.5
|
Submit date:2023/08/03
Bang-bang Clock And Data Recovery (Bbcdr)
Wide Capture Range
Single Loop
Frequency Detector (Fd)
Hybrid Control Circuit (Hcc)
Deliberate Current Mismatch
Ring Oscillator (Ro)
R-2r Dac
Positive (Pnc)
Negative (Nnc) And Zero (Znc) Net Current
Cmos
Bang-bang Phase Detector (Bbpd)
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation
Journal article
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhou, Xionghui, Han, Mei, Stefano, Crovetti Paolo, Mak, Pui In, Martins, Rui P.. A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation[J]. International Journal of Circuit Theory and Applications, 2023, 51(5), 1988-2015.
Authors:
Wang, Lin
;
Chen, Yong
;
Yang, Chaowei
;
Zhou, Xionghui
;
Han, Mei
; et al.
Favorite
|
TC[WOS]:
1
TC[Scopus]:
2
IF:
1.8
/
1.7
|
Submit date:2023/06/05
Bang-bang Clock And Data Recovery (Bbcdr)
Current Mismatch
Frequency Detector (Fd)
Hybrid Control Circuit (Hcc)
Phase Interpolator (Pi)
R-2r Digital-to-analog Converter (Dac)
Ring Oscillator (Ro)
Switched-capacitor (Sc) Array
Wide Capture Range
A 0.15-V, 44.73% PCE charge pump with CMOS differential ring-VCO for energy harvesting systems
Journal article
Pakkirisami Churchill, Kishore Kumar, Ramiah, Harikrishnan, Chong, Gabriel, Ahmad, Mohd Yazed, Yin, Jun, Mak, Pui In, Martins, Rui P.. A 0.15-V, 44.73% PCE charge pump with CMOS differential ring-VCO for energy harvesting systems[J]. Analog Integrated Circuits and Signal Processing, 2022, 111(1), 35-43.
Authors:
Pakkirisami Churchill, Kishore Kumar
;
Ramiah, Harikrishnan
;
Chong, Gabriel
;
Ahmad, Mohd Yazed
;
Yin, Jun
; et al.
Favorite
|
TC[WOS]:
6
TC[Scopus]:
8
IF:
1.2
/
1.0
|
Submit date:2022/05/04
Charge Pump
Dc-to-dc Conversion
Dynamic Voltage Frequency Scaling (Dvfs)
Energy Harvesting
Ring-voltage ContRolled Oscillator (Ro)
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme
Conference paper
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhao, Xiaoteng, Mak, Pui In, Maloberti, Franco, Martins, Rui P.. A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2022.
Authors:
Wang, Lin
;
Chen, Yong
;
Yang, Chaowei
;
Zhao, Xiaoteng
;
Mak, Pui In
; et al.
Favorite
|
TC[WOS]:
1
TC[Scopus]:
1
|
Submit date:2023/03/06
Hybrid Control Circuit (Hcc)
Deliberate Current Mismatch
Charge Pump (Cp)
Ring Oscillator (Ro)
R-2r Dac
Positive (Pnc)
Negative (Nnc)
Zero (Znc) Net Current
A 0.01-mm21.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase
Conference paper
Zhao, Xiaoteng, Chen, Yong, Zheng, Xuqiang, Mak, Pui In, Martins, Rui P.. A 0.01-mm21.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase[C], 2021, 386-389.
Authors:
Zhao, Xiaoteng
;
Chen, Yong
;
Zheng, Xuqiang
;
Mak, Pui In
;
Martins, Rui P.
Favorite
|
TC[WOS]:
6
TC[Scopus]:
4
|
Submit date:2021/12/08
Bang-bang Clock And Data Recovery (Bbcdr)
Clock Selection
Cmos
Frequency Acquisition
Frequency Detector (Fd)
Reference (Ref)
Ring Oscillator (Ro)
Strobe Point (Sp)