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A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh Journal article
Zhan, Yi, Yu, Wei Han, Un, Ka Fai, Martins, Rui P., Mak, Pui In. A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh[J]. IEEE Journal of Solid-State Circuits, 2024, 59(11), 3866-3876.
Authors:  Zhan, Yi;  Yu, Wei Han;  Un, Ka Fai;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/05/16
Compute-in-memory (Cim)  Deep Neural Network (Dnn)  Embedded Dynamic Random Access Memory (Edram)  Input-sparsity  Single-finger (Sf)  Weight Update/refresh  
Interfacial magnetic spin Hall effect in van der Waals Fe3GeTe2/MoTe2 heterostructure Journal article
Dai, Yudi, Xiong, Junlin, Ge, Yanfeng, Cheng, Bin, Wang, Lizheng, Wang, Pengfei, Liu, Zenglin, Yan, Shengnan, Zhang, Cuiwei, Xu, Xianghan, Shi, Youguo, Cheong, Sang Wook, Xiao, Cong, Yang, Shengyuan A., Liang, Shi Jun, Miao, Feng. Interfacial magnetic spin Hall effect in van der Waals Fe3GeTe2/MoTe2 heterostructure[J]. Nature Communications, 2024, 15(1), 1129.
Authors:  Dai, Yudi;  Xiong, Junlin;  Ge, Yanfeng;  Cheng, Bin;  Wang, Lizheng; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:14.7/16.1 | Submit date：2024/05/16
Random-access Memory  
34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC Conference paper
Yuan, Yiyang, Yang, Yiming, Wang, Xinghua, Li, Xiaoran, Ma, Cailian, Chen, Qirui, Tang, Meini, Wei, Xi, Hou, Zhixian, Zhu, Jialiang, Wu, Hao, Ren, Qirui, Xing, Guozhong, Mak, Pui In, Zhang, Feng. 34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 576-578.
Authors:  Yuan, Yiyang;  Yang, Yiming;  Wang, Xinghua;  Li, Xiaoran;  Ma, Cailian; et al.
Favorite | TC[Scopus]:2 | Submit date：2024/05/16
Training  Random Access Memory  Throughput  Common Information Model (Computing)  System-on-chip  Solid State Circuits  Complexity Theory  
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications Journal article
Zhao, Zhongyu, Cao, Rujian, Un, Ka Fai, Yu, Wei Han, Mak, Pui In, Martins, Rui P.. An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(1), 281-285.
Authors:  Zhao, Zhongyu;  Cao, Rujian;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In; et al.
Favorite | TC[WOS]:8 TC[Scopus]:12  IF:4.0/3.7 | Submit date：2022/08/08
Transformers  Energy Efficiency  Broadcasting  Convolutional Neural Networks  Integrated Circuit Modeling  Field Programmable Gate Arrays  Random Access Memory  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Energy Efficiency  Image Recognition  Transformer  
An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition Journal article
Lei Xuan, Ka-Fai Un, Chi-Seng Lam, Rui P. Martins. An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(10), 4003-4007.
Authors:  Lei Xuan;  Ka-Fai Un;  Chi-Seng Lam;  Rui P. Martins
Favorite | TC[WOS]:26 TC[Scopus]:26  IF:4.0/3.7 | Submit date：2022/06/14
Frequency Modulation  Field Programmable Gate Arrays  Energy Efficiency  Memory Management  Random Access Memory  Arrays  Computational Cost  Convolutional Neural Network (Cnn)  Field-programmable Gate Array (Fpga)  Mobilenetv2  Neural Network  Quantization  
A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise Journal article
Zhao,Qiang, Zheng,Wenhan, Zhao,Xiaojin, Cao,Yuan, Zhang,Feng, Law,Man Kay. A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67(11), 3866-3879.
Authors:  Zhao,Qiang;  Zheng,Wenhan;  Zhao,Xiaojin;  Cao,Yuan;  Zhang,Feng; et al.
Favorite | TC[WOS]:25 TC[Scopus]:26  IF:5.2/4.5 | Submit date：2021/03/11
Dynamic Entropy Source  Full Reconfigurability  High Reliability  Physical Unclonable Function  Resistive Random Access Memory  True Random Number Generator