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A 140 pW, -77 dB PSRR, PMOS-Only Voltage Reference Using Pre-Regulation Technique with Gate and Bulk Feedback Journal article
Li, Sizhen, Qiu, Yuhao, Yu, Kai, Huang, Mo. A 140 pW, -77 dB PSRR, PMOS-Only Voltage Reference Using Pre-Regulation Technique with Gate and Bulk Feedback[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024.
Authors:  Li, Sizhen;  Qiu, Yuhao;  Yu, Kai;  Huang, Mo
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2025/01/13
Voltage Reference  Power Supply Rejection Ratio  Line Sensitivity  Pre-regulation  Low-power  
A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control Journal article
Yu, Kai, Yang, Shangru, Li, Sizhen, Huang, Mo. A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(4), 1754-1758.
Authors:  Yu, Kai;  Yang, Shangru;  Li, Sizhen;  Huang, Mo
Favorite | TC[WOS]:3 TC[Scopus]:4  IF:4.0/3.7 | Submit date：2024/05/02
Cmos Voltage Reference  Dibl Effect Compensation  Line Sensitivity  Power Supply Rejection Ratio  Self-biased  Ultra-low Power  
A 0.011%/V LS and −76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror Journal article
Yu, Kai, Chen, Jiyang, Li, Sizhen, Huang, Mo. A 0.011%/V LS and −76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(3), 1052-1056.
Authors:  Yu, Kai;  Chen, Jiyang;  Li, Sizhen;  Huang, Mo
Favorite | TC[WOS]:3 TC[Scopus]:4  IF:4.0/3.7 | Submit date：2024/02/22
Cmos Voltage Reference  Line Sensitivity  Power Supply Rejection Ratio  Quasi Self-cascode Current Mirror  Self-biased  
A 13-bit 8-kS/s δ ∑ Readout IC Using ZCB Integrators with an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR Journal article
Li,Bing, Na,Ji Ping, Wang,Wei, Liu,Jia, Yang,Qian, Mak,Pui In. A 13-bit 8-kS/s δ ∑ Readout IC Using ZCB Integrators with an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(4), 843-853.
Authors:  Li,Bing;  Na,Ji Ping;  Wang,Wei;  Liu,Jia;  Yang,Qian; et al.
Favorite | TC[WOS]:10 TC[Scopus]:13  IF:2.8/2.8 | Submit date：2020/12/04
Cmos  Figure Of Merit (Fom)  Oversampling Δ-ς Modulation  Power-supply Rejection Ratio (Psrr)  Readout Ic (roIc)  Resistive Sensor  Wheatstone Bridge  Zero-crossing-based (Zcb) Integrator