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Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial V-cm-Based Switching Journal article
Xing, Dezhi, Zhu, Yan, Chan, Chi-Hang, Sin, Sai-Weng, Ye, Fan, Ren, Junyan, U, Seng-Pan, Martins, Rui Paulo. Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial V-cm-Based Switching[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25(3), 1168-1172.
Authors:  Xing, Dezhi;  Zhu, Yan;  Chan, Chi-Hang;  Sin, Sai-Weng;  Ye, Fan; et al.
Favorite | TC[WOS]:14 TC[Scopus]:17  IF:2.8/2.8 | Submit date：2018/10/30
Common Mode Variation  Partial V-cm-based Switching  Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)