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A 21.8-41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller Journal article
Chen, Wen, Shu, Yiyang, Yin, Jun, Mak, Pui In, Gao, Xiang, Luo, Xun. A 21.8-41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller[J]. IEEE Transactions on Microwave Theory and Techniques, 2024.
Authors:  Chen, Wen;  Shu, Yiyang;  Yin, Jun;  Mak, Pui In;  Gao, Xiang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.1/4.2 | Submit date：2024/05/16
Detectors  Fast Locking  Frequency Locked Loops  Jitter  Jitter  Millimeter Wave (mm-Wave)  Phase Locked Loops  Phase Noise  Subsampling Phase-locked Loop (Sspll)  Voltage-controlled Oscillators  Wideband  Wideband  
A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoMT in 65-nm CMOS Journal article
Zhao, Ya, Fan, Chao, Peng, Yuanxing, Liang, Chenglong, Yin, Jun, Mak, Pui In, Geng, Li. A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoMT in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(5), 2604-2608.
Authors:  Zhao, Ya;  Fan, Chao;  Peng, Yuanxing;  Liang, Chenglong;  Yin, Jun; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2024/05/16
Couplings  Dual-core  Dual-mode  Frequency Tuning Range (Ftr)  Inductance  Layout  Millimeter-wave (Mm-wave)  Mode-switching  Multi-coil  Phase Noise (Pn)  Transformer Cores  Transformers  Tuning  Voltage-controlled Oscillator (Vco)  Voltage-controlled Oscillators  
A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS Journal article
Lu, Xin, Wu, Jiangchao, Wang, Zhao, Xiang, Yifei, Liu, Liyuan, Mak, Pui In, Martins, Rui P., Law, Man Kay. A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(8), 3635 - 3639.
Authors:  Lu, Xin;  Wu, Jiangchao;  Wang, Zhao;  Xiang, Yifei;  Liu, Liyuan; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2024/05/16
Coarse-fine Conversion  Cyclic Time-to-digital Converter (Tdc)  Delays  Gated-ring Oscillator (Gro)  Generators  Image Edge Detection  Logic Gates  Phase Domain Reset  Ring Oscillators  Signal Resolution  Switches  
A 28 nm 368 fJ/cycle, 0.43%/V Supply Sensitivity, FLL based RC Oscillator Featuring Positive TC Only Resistors and ΣM Based Trimming Journal article
Huang,Yunbo, Chen,Yong, Yang,Kaiyuan, Crovetti,Paolo, Mak,Pui In, Martins,Rui P.. A 28 nm 368 fJ/cycle, 0.43%/V Supply Sensitivity, FLL based RC Oscillator Featuring Positive TC Only Resistors and ΣM Based Trimming[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(11), 3950-3954.
Authors:  Huang,Yunbo;  Chen,Yong;  Yang,Kaiyuan;  Crovetti,Paolo;  Mak,Pui In; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2023/08/03
Clocks  Cmos  Delta-sigma-modulator  Energy Efficiency  Frequency Inaccuracy  Frequency-locked-loop (Fll)  Generators  Oscillators  Rc Oscillator  Resistance  Resistors  Switched-capacitor Resistor  Switches  Temperature Coefficients  Voltage-controlled Oscillators  
Some new results on the consensus of coupled harmonic oscillators with impulsive control Journal article
Yao, Zhongsheng, Vong, Seakweng. Some new results on the consensus of coupled harmonic oscillators with impulsive control[J]. International Journal of Robust and Nonlinear Control, 2022, 32(4), 1960-1972.
Authors:  Yao, Zhongsheng;  Vong, Seakweng
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:3.2/3.5 | Submit date：2022/03/28
Consensus  Coupled Harmonic Oscillators  Impulsive Control  Joint Spectral Radius  Sampled Position Data  
A Swing-Enhanced Class-D VCO Using a Periodically Time-Varying (PTV) Inductor Journal article
Lin, Xiaoqi, Yin, Jun, Mak, Pui In, Martins, Rui P.. A Swing-Enhanced Class-D VCO Using a Periodically Time-Varying (PTV) Inductor[J]. IEEE Solid-State Circuits Letters, 2022, 5, 25-28.
Authors:  Lin, Xiaoqi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:5 TC[Scopus]:5 | Submit date：2022/05/17
Inductors  Voltage-controlled Oscillators  Voltage  Capacitors  Resonant Frequency  Transistors  Transformers  
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
Liu, Yueduo, Bao, Rongxin, Zhu, Zihao, Yang, Shiheng, Zhou, Xiong, Li, Qiang, Yin, Jun, Mak, Pui In. Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(2), 495-505.
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2022/03/04
Voltage-controlled Oscillators  Jitter  Clocks  Phase Noise (Pn)  Topology  Performance Evaluation  Delays  Figure Of Merit (Fom)  Injection-locked Clock Multiplier (Ilcm)  Multiplying Delay-locked Loop (Mdll)  Power  Ring Voltage-controlled Oscillator (Rvco)  
Adaptive Fourier Decomposition for Multi-Channel Signal Analysis Journal article
Wang Ze, Wong Chi Man, Agostinho Rosa, Qian Tao, Wan F(萬峰). Adaptive Fourier Decomposition for Multi-Channel Signal Analysis[J]. IEEE Transactions on Signal Processing, 2022, 70, 903-918.
Authors:  Wang Ze;  Wong Chi Man;  Agostinho Rosa;  Qian Tao;  Wan F(萬峰)
Adobe PDF | Favorite | TC[WOS]:12 TC[Scopus]:6  IF:4.6/5.2 | Submit date：2022/08/28
Time-frequency Analysis  Oscillators  Convergence  Wavelet Transforms  Adaptation Models  Frequency Modulation  Chirp  Amplitude And Frequency Modulated Signal  Adaptive Fourier Decomposition  Multi-channel Signal  Time-frequency Analysis  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
Zhao, Xiaoteng, Chen, Yong, Mak, Pui In, Martins, Rui P.. A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 57(2), 546-561.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:4.6/5.6 | Submit date：2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
A 0.35-V 5,200-μm² 2.1-MHz Temperature- Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator Journal article
Ka-Meng Lei, Pui-In Mak, Rui P. Martins. A 0.35-V 5,200-μm² 2.1-MHz Temperature- Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator[J]. IEEE Journal of Solid-State Circuits, 2021, 56(9), 2701 - 2710.
Authors:  Ka-Meng Lei;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:21 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2021/09/20
Asymmetric Rc Network  Circuit Stability  Cmos  Energy-harvesting  Internet-of-things (Iot)  Logic Gates  Mos Devices  Oscillators  Relaxation Oscillator (Rxo)  Resilience  Stability Criteria  Swing-boosting  Temperature Resilience  Thermal Stability  Ultra-low-power  Ultra-low-voltage (Ulv).