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A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity Journal article
Wu, Hao, Chen, Yong, Yuan, Yiyang, Yue, Jinshan, Fu, Xiangqu, Ren, Qirui, Luo, Qing, Mak, Pui In, Wang, Xinghua, Zhang, Feng. A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 71(2), 689-702.
Authors:  Wu, Hao;  Chen, Yong;  Yuan, Yiyang;  Yue, Jinshan;  Fu, Xiangqu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/02/22
Algebraic Sparsity (As)  Cmos  Computing-in-memory (Cim)  Multiply-accumulation (Mac)  Structured Sparsity (Ss)  Super-resolution (Sr)  Texture Sparsity (Ts)  
A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity Journal article
Wu, Hao, Chen, Yong, Yuan, Yiyang, Yue, Jinshan, Wang, Xinghua, Li, Xiaoran, Zhang, Feng. A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Wu, Hao;  Chen, Yong;  Yuan, Yiyang;  Yue, Jinshan;  Wang, Xinghua; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/07/04
Accuracy  Artificial Intelligence  Artificial Intelligence (Ai)  Circuits  Cmos  Computing-in-memory (Cim)  Energy Efficiency  Energy Efficiency  Look-up Table (Lut)  Multiply-accumulation (Mac)  Neural Network (Nn)  Power Demand  Radix16  Table Lookup  Throughput  Unstructured Sparsity  Winograd Convolution