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A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin Journal article
Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui P. Martins. A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(9), 3014-3026.
Authors:  Yong Chen;  Pui-In Mak;  Chirn Chye Boon;  Rui P. Martins
Favorite | TC[WOS]:26 TC[Scopus]:29  IF:5.2/4.5 | Submit date：2019/02/11
Bandwidth (Bw)  Cmos  Cross-quadrature Clocking  D-type Flip-flop (Dff)  Data-dependent Jitter (Ddj)  Duobinary  Figure-of-merit (Fom)  Latch  Multi-level Signaling  Multiplexer (Mux)  Selector  Timing Margin  
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin Journal article
Chen, Y., Mak, P. I., Boon, C.C., Martins, R. P.. A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 3014-3026.
Authors:  Chen, Y.;  Mak, P. I.;  Boon, C.C.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
Bandwidth (BW)  cross-quadrature clocking  data- dependent jitter (DDJ)  duobinary  multi-level signaling  CMOS  multiplexer (MUX)  figure-of-merit (FOM)  timing margin  latch  D-type flip-flop (DFF)  selector