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An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs
Conference paper
Li D., Sin S.-W., Seng-Pan U., Martins R.P.. An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs[C], 2010, 208-211.
Authors:
Li D.
;
Sin S.-W.
;
Seng-Pan U.
;
Martins R.P.
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Submit date：2019/02/11
Capacitor Mismatch
Digital Calibration
Interstage Gain Error
Pipelined Adcs
