×
验证码:
换一张
Forgotten Password?
Stay signed in
Login With UMPASS
English
|
繁體
Login With UMPASS
Log In
ALL
ORCID
TI
AU
PY
SU
KW
TY
JN
DA
IN
PB
FP
ST
SM
Study Hall
Image search
Paste the image URL
Home
Faculties & Institutes
Scholars
Publications
Subjects
Statistics
News
Search in the results
Faculties & Institutes
Faculty of Scien... [4]
THE STATE KEY LA... [2]
INSTITUTE OF MIC... [2]
Authors
RUI PAULO DA SIL... [1]
MAK PUI IN [1]
VAI MANG I [1]
CHENGZHONG XU [1]
MAK PENG UN [1]
UN KA FAI [1]
More...
Document Type
Conference paper [2]
Journal article [2]
Date Issued
2024 [1]
2022 [1]
2019 [1]
2010 [1]
Language
英語English [4]
Source Publication
IEEE Transaction... [1]
IEEE Transaction... [1]
Proceedings - 20... [1]
Proceedings - 20... [1]
Indexed By
SCIE [3]
CPCI-S [1]
Funding Organization
Funding Project
×
Knowledge Map
UM
Start a Submission
Submissions
Unclaimed
Claimed
Attach Fulltext
Bookmarks
Browse/Search Results:
1-4 of 4
Help
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Issue Date Ascending
Issue Date Descending
Title Ascending
Title Descending
Author Ascending
Author Descending
WOS Cited Times Ascending
WOS Cited Times Descending
Submit date Ascending
Submit date Descending
Journal Impact Factor Ascending
Journal Impact Factor Descending
An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications
Journal article
Cao, Rujian, Zhao, Zhongyu, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(11), 4688-4692.
Authors:
Cao, Rujian
;
Zhao, Zhongyu
;
Un, Ka Fai
;
Yu, Wei Han
;
Martins, Rui P.
; et al.
Favorite
|
TC[WOS]:
0
TC[Scopus]:
0
IF:
4.0
/
3.7
|
Submit date:2024/10/10
Sparse Matrices
Computational Modeling
Transformers
Hardware
Energy Efficiency
Circuits
Throughput
Dataflow
Digital Accelerator
Energy-efficient
Field-programmable Gate Array (Fpga)
Sparsity
Transformer
An Energy-Efficient SIFT Based Feature Extraction Accelerator for High Frame-Rate Video Applications
Journal article
Liu, Bingqiang, Yin, Zehua, Zhang, Xvpeng, Zhan, Yi, Hu, Xiaofeng, Yu, Guoyi, Zheng, Yuanjin, Wang, Chao, Zou, Xuecheng. An Energy-Efficient SIFT Based Feature Extraction Accelerator for High Frame-Rate Video Applications[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(12), 4930-4943.
Authors:
Liu, Bingqiang
;
Yin, Zehua
;
Zhang, Xvpeng
;
Zhan, Yi
;
Hu, Xiaofeng
; et al.
Favorite
|
TC[WOS]:
7
TC[Scopus]:
9
IF:
5.2
/
4.5
|
Submit date:2023/02/27
Feature Extraction
Scale-invariant Feature Transform (Sift)
High Frame Rate
Hardware Accelerator
Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs
Conference paper
Zhao,Yiren, Gao,Xitong, Guo,Xuan, Liu,Junyi, Wang,Erwei, Mullins,Robert, Cheung,Peter Y.K., Constantinides,George, Xu,Cheng Zhong. Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs[C], IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA:IEEE, 2019, 45-53.
Authors:
Zhao,Yiren
;
Gao,Xitong
;
Guo,Xuan
;
Liu,Junyi
;
Wang,Erwei
; et al.
Favorite
|
TC[WOS]:
25
TC[Scopus]:
31
|
Submit date:2021/03/09
Auto-generation
Cnn Hardware Accelerator
Hardware-accelerated implementation of EMD
Conference paper
Wang L., Vai M.I., Mak P.U., Ieong C.I.. Hardware-accelerated implementation of EMD[C], 2010, 912-915.
Authors:
Wang L.
;
Vai M.I.
;
Mak P.U.
;
Ieong C.I.
Favorite
|
TC[WOS]:
13
TC[Scopus]:
28
|
Submit date:2019/02/14
Emd
Fpga
Hardware Accelerator
Hht
Imf
Nios Ii