Residential College | false |
Status | 已發表Published |
Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs | |
Zhao,Yiren1; Gao,Xitong2; Guo,Xuan1; Liu,Junyi3; Wang,Erwei4; Mullins,Robert1; Cheung,Peter Y.K.4; Constantinides,George4; Xu,Cheng Zhong5 | |
2019-12-01 | |
Conference Name | 18th International Conference on Field-Programmable Technology, ICFPT 2019 |
Source Publication | Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019 |
Volume | 2019-December |
Pages | 45-53 |
Conference Date | DEC 09-13, 2019 |
Conference Place | Tianjin, China |
Country | China |
Publication Place | IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA |
Publisher | IEEE |
Abstract | Modern deep Convolutional Neural Networks (CNNs) are computationally demanding, yet real applications often require high throughput and low latency. To help tackle these problems, we propose Tomato, a framework designed to automate the process of generating efficient CNN accelerators. The generated design is pipelined and each convolution layer uses different arithmetics at various precisions. Using Tomato, we showcase state-of-the-art multi-precision multi-arithmetic networks, including MobileNet-V1, running on FPGAs. To our knowledge, this is the first multi-precision multi-arithmetic autogeneration framework for CNNs. In software, Tomato fine-tunes pretrained networks to use a mixture of short powers-of-2 and fixed-point weights with a minimal loss in classification accuracy. The fine-tuned parameters are combined with the templated hardware designs to automatically produce efficient inference circuits in FPGAs. We demonstrate how our approach significantly reduces model sizes and computation complexities, and permits us to pack a complete ImageNet network onto a single FPGA without accessing off-chip memories for the first time. Furthermore, we show how Tomato produces implementations of networks with various sizes running on single or multiple FPGAs. To the best of our knowledge, our automatically generated accelerators outperform closest FPGA-based competitors by at least 2-4× for lantency and throughput; the generated accelerator runs ImageNet classification at a rate of more than 3000 frames per second. |
Keyword | Auto-generation Cnn Hardware Accelerator |
DOI | 10.1109/ICFPT47387.2019.00014 |
URL | View the original |
Indexed By | CPCI-S |
Language | 英語English |
WOS Research Area | Computer Science ; Engineering |
WOS Subject | Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic |
WOS ID | WOS:000574770300006 |
Scopus ID | 2-s2.0-85083037366 |
Fulltext Access | |
Citation statistics | |
Document Type | Conference paper |
Collection | Faculty of Science and Technology |
Co-First Author | Zhao,Yiren; Gao,Xitong |
Corresponding Author | Zhao,Yiren |
Affiliation | 1.University of Cambridge,United Kingdom 2.Shenzhen Institutes of Advanced Technology, China 3.Microsoft Research Cambridge, United States 4.Imperial College London, United Kingdom 5.University of Macau, Macao |
Recommended Citation GB/T 7714 | Zhao,Yiren,Gao,Xitong,Guo,Xuan,et al. Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs[C], IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA:IEEE, 2019, 45-53. |
APA | Zhao,Yiren., Gao,Xitong., Guo,Xuan., Liu,Junyi., Wang,Erwei., Mullins,Robert., Cheung,Peter Y.K.., Constantinides,George., & Xu,Cheng Zhong (2019). Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs. Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019, 2019-December, 45-53. |
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