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A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors Conference paper
Zhang, Minglei, Cao, Yuefeng, Zhu, Yan, Chan, Chi-Hang, Martins, R. P.. A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors[C]:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Zhang, Minglei;  Cao, Yuefeng;  Zhu, Yan;  Chan, Chi-Hang;  Martins, R. P.
Favorite | TC[Scopus]:2 | Submit date：2023/07/12
Dynamic Amplifier  Residue Amplifier  Pipelined-sar Adc  Linearization Technique  Bypass Capacitor  
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier Journal article
Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi Hang Chan, Jan Craninckx, Rui P. Martins. A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier[J]. IEEE Journal of Solid-State Circuits, 2021.
Authors:  Zihao Zheng;  Lai Wei;  Jorge Lagos;  Ewout Martens;  Yan Zhu; et al.
Favorite | TC[WOS]:8 TC[Scopus]:9  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Conversion  Calibration  Calibration  Dynamic Amplifier (Da)  Hardware  Linearity  Linearization Technique  Pipeline Processing  Pipelined Analog-to-digital Converter (Adc).  Quantization (Signal)  Signal Resolution  System-on-chip  
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
Zheng, Z., Wei, W., Lagos, J., Martens, E., Zhu, Y., Chan, C. H., Craninckx, J., Martins, R. P.. 16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation[C], 2020.
Authors:  Zheng, Z.;  Wei, W.;  Lagos, J.;  Martens, E.;  Zhu, Y.; et al.
Favorite |  | Submit date：2022/01/25
Amplifiers  Analogue-digital Conversion  Calibration  Interpolation  Dynamic Pipelined Adc  Dynamic Pipelined Architecture  Linearized Dynamic Amplifier  Post-amplification Residue Generation Scheme  Residue Amplification  Complex Residue-transferring Realization  Residue Amplifier  Power Consumption  Sar Adc  Calibration Complexity  Aggressive Interpolation Factor  Flash Adc  Mm-wave 5g Receivers  Adc-based Serial Links  Power 5.5 Mw  Calibration  Quantization (Signal)  Clocks  System-on-chip  Interpolation  Prototype  
An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS Journal article
Zhang, Jin, Ren, Xiaoqian, Liu, Shubin, Chan, Chi Hang, Zhu, Zhangming. An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 67(7), 1174-1178.
Authors:  Zhang, Jin;  Ren, Xiaoqian;  Liu, Shubin;  Chan, Chi Hang;  Zhu, Zhangming
Favorite | TC[WOS]:9 TC[Scopus]:18  IF:4.0/3.7 | Submit date：2021/12/06
Analog-to-digital Converter (Adc)  Full Dynamic Adc  Pipelined Successive-approximation-register (Sar)  Pvt-stabilized Dynamic Amplification  Reused Comparator