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A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling Conference paper
Wang, Qingxun, Pan, Yuhan, Chen, Kaiquan, Lin, Yu, Wang, Biao, Qi, Liang. A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling[C]:IEEE345 E 47TH ST, NEW YORK, NY 10017 USA, 2023.
Authors:  Wang, Qingxun;  Pan, Yuhan;  Chen, Kaiquan;  Lin, Yu;  Wang, Biao; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/02/23
Incremental Analog-to-digital Converter (Iadc)  Linear-exponential  Second-order Noise Coupling (Nc)  The Effective Data Weighting Averaging (Dwa) And Suppression Of Thermal Noise  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
Jiang, Dongyang, Qi, Liang, Sin, Sai Weng, Maloberti, Franco, Martins, Rui P.. A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56(8), 2375-2387.
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite | TC[WOS]:15 TC[Scopus]:17  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
Discrete-time mash delta-sigma modulator with second-order digital noise coupling for wideband high-resolution applications Conference paper
Qin, Xinyu, Zhang, Jingying, Qi, Liang, Sin, Sai Weng, Martins, Rui P., Wang, Guoxing. Discrete-time mash delta-sigma modulator with second-order digital noise coupling for wideband high-resolution applications[C], 2021.
Authors:  Qin, Xinyu;  Zhang, Jingying;  Qi, Liang;  Sin, Sai Weng;  Martins, Rui P.; et al.
Favorite | TC[WOS]:2 TC[Scopus]:9 | Submit date：2021/09/20
Digital Noise Coupling  Multistage Noise Shaping (Mash)  Noise Leakage  Wideband High-resolution Applications  Δς Modulator (Dsm)  
A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
Qi, L., Jain, A., Jiang, D., Sin, S. W., Martins, R. P., Ortmanns, M.. A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355.
Authors:  Qi, L.;  Jain, A.;  Jiang, D.;  Sin, S. W.;  Martins, R. P.; et al.
Favorite | TC[WOS]:56 TC[Scopus]:51  IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
Qi,Liang, Jain,Ankesh, Jiang,Dongyang, Sin,Sai Weng, Martins,Rui P., Ortmanns,Maurits. A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355.
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.; et al.
Favorite | TC[WOS]:56 TC[Scopus]:51  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)