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Interactive IIR SC multirate compiler applied to multistage decimator design Journal article
PHILLIP N. CHEONG, R. P. MARTINS. Interactive IIR SC multirate compiler applied to multistage decimator design[J]. Journal of Circuits, Systems and Computers, 2007, 16(4), 517-525.
Authors:  PHILLIP N. CHEONG;  R. P. MARTINS
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:0.9/0.9 | Submit date：2019/02/11
Iir Filter  Multistage  Switched Capacitors  Decimator Design  Compiler  
A novel algorithm for automated optimum design of IIR SC decimators Journal article
Ngai C., Martins R.P., Franca J.E.. A novel algorithm for automated optimum design of IIR SC decimators[J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2002, 49(4), 293-296.
Authors:  Ngai C.;  Martins R.P.;  Franca J.E.
Favorite | TC[WOS]:3 TC[Scopus]:6 | Submit date：2019/02/11
Automated Optimum Design  Infinite-impulse Response (Iir) Switched-capacitor (Sc) Decimator  Linear/nonlinear Programming