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CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization Journal article
Fu, Yuzhao, Li, Jixuan, Yu, Wei Han, Un, Ka Fai, Chan, Chi Hang, Zhu, Yan, Martins, Rui P., Mak, Pui In. CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization[J]. IEEE Transactions on Circuits and Systems I-Regular Papers, 2024, 71(11), 4996-5004.
Authors:  Fu, Yuzhao;  Li, Jixuan;  Yu, Wei Han;  Un, Ka Fai;  Chan, Chi Hang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/07/04
Capacitance Lookup Table (Clut)  Circuits  Common Information Model (Computing)  Compute-in-memory (Cim)  Energy Efficiency  High Energy Efficiency  In-memory Computing  Indexes  Nonuniform Quantization (Nuq)  Table Lookup  Thermometers  Weight Updating  
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity Journal article
Wu, Hao, Chen, Yong, Yuan, Yiyang, Yue, Jinshan, Fu, Xiangqu, Ren, Qirui, Luo, Qing, Mak, Pui In, Wang, Xinghua, Zhang, Feng. A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 71(2), 689-702.
Authors:  Wu, Hao;  Chen, Yong;  Yuan, Yiyang;  Yue, Jinshan;  Fu, Xiangqu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2024/02/22
Algebraic Sparsity (As)  Cmos  Computing-in-memory (Cim)  Multiply-accumulation (Mac)  Structured Sparsity (Ss)  Super-resolution (Sr)  Texture Sparsity (Ts)  
A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity Journal article
Wu, Hao, Chen, Yong, Yuan, Yiyang, Yue, Jinshan, Wang, Xinghua, Li, Xiaoran, Zhang, Feng. A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Wu, Hao;  Chen, Yong;  Yuan, Yiyang;  Yue, Jinshan;  Wang, Xinghua; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/07/04
Accuracy  Artificial Intelligence  Artificial Intelligence (Ai)  Circuits  Cmos  Computing-in-memory (Cim)  Energy Efficiency  Energy Efficiency  Look-up Table (Lut)  Multiply-accumulation (Mac)  Neural Network (Nn)  Power Demand  Radix16  Table Lookup  Throughput  Unstructured Sparsity  Winograd Convolution  
P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer Journal article
Fu, Xiangqu, Ren, Qirui, Wu, Hao, Xiang, Feibin, Luo, Qing, Yue, Jinshan, Chen, Yong, Zhang, Feng. P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4938-4948.
Authors:  Fu, Xiangqu;  Ren, Qirui;  Wu, Hao;  Xiang, Feibin;  Luo, Qing; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:5.2/4.5 | Submit date：2024/02/22
Accelerator  Cmos  Computing-in-memory (Cim)  Dynamic Prune  Prediction Network  Vision Transformer (Vit)