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Ring-VCO-based Phase-Locked Loops for Clock Generation – Design Considerations and State-of-the-Art Journal article
Shiheng Yang, Jun Yin, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Qiang Li, Pui-In Mak, Rui P. Martins. Ring-VCO-based Phase-Locked Loops for Clock Generation – Design Considerations and State-of-the-Art[J]. Chip, 2023, 2(2), 1-10.
Authors:  Shiheng Yang;  Jun Yin;  Yueduo Liu;  Rongxin Bao;  Zihao Zhu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:3 | Submit date：2023/08/19
Clock Generation, Ic Design, Phase-locked Loop (Pll), Frequency Synthesizer