This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different applications. Partic- ularly, the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power, jitter and area. An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt- ically and benchmarked with respect to their figure-of-merit (FoM). The paper also summarizes the key concerns on the selection of dif- ferent circuit techniques to optimize the clock performance under dif- ferent scenarios.