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An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
Cao, Rujian, Zhao, Zhongyu, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(11), 4688-4692.
Authors:  Cao, Rujian;  Zhao, Zhongyu;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/10/10
Sparse Matrices  Computational Modeling  Transformers  Hardware  Energy Efficiency  Circuits  Throughput  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Sparsity  Transformer  
A wideband dual-band bandstop filter with flexible control of stopband rejection, bandwidth and centre frequency ratio Journal article
Xu, Chang, Wang, Xiaolong, Zhu, Lei, Sun, Wenzhong, Li, Kun, Milinevsky, Gennadi, Lu, Geyu. A wideband dual-band bandstop filter with flexible control of stopband rejection, bandwidth and centre frequency ratio[J]. IET MICROWAVES ANTENNAS & PROPAGATION, 2024, 18(5), 308-316.
Authors:  Xu, Chang;  Wang, Xiaolong;  Zhu, Lei;  Sun, Wenzhong;  Li, Kun; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.1/1.4 | Submit date：2024/06/05
Adaptive Filters  Band-stop Filters  Coupled Transmission Lines  Filtering Theory  Filters  Microstrip Circuits  Microstrip Filters  Microwave Circuits  Microwave Filters  Passive Filters  
A Battery-Input Three-Mode Buck–Boost Hybrid DC–DC Converter With 97.6% Peak Efficiency Journal article
Zhao, Shuangxing, Zhan, Chenchang, Lu, Yan. A Battery-Input Three-Mode Buck–Boost Hybrid DC–DC Converter With 97.6% Peak Efficiency[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024, 59(5), 1567-1577.
Authors:  Zhao, Shuangxing;  Zhan, Chenchang;  Lu, Yan
Favorite | TC[WOS]:3 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/02/22
33-v Devices  Flying Capacitor  Lithium-ion (Li-ion) Batteries  Low Electromagnetic Interference (Emi)  Soft-startup Circuits  Three-mode Non-inverting Buck–boost Hybrid Converter (3m-bbhc)  
28.3 A 12-28V to 0.6-1.8V Ratio-Regulatable Dickson SC Converter with Dual-Mode Phase Misalignment Operations Achieving 93.1% Efficiency and 6A Output Conference paper
Ma, Qiaobo, Jiang, Yang, Li, Huihua, Zhang, Xiongjie, Law, Man Kay, Martins, Rui P., Mak, Pui In. 28.3 A 12-28V to 0.6-1.8V Ratio-Regulatable Dickson SC Converter with Dual-Mode Phase Misalignment Operations Achieving 93.1% Efficiency and 6A Output[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 460-462.
Authors:  Ma, Qiaobo;  Jiang, Yang;  Li, Huihua;  Zhang, Xiongjie;  Law, Man Kay; et al.
Favorite | TC[Scopus]:1 | Submit date：2024/05/16
Switches  Universal Serial Bus  Regulation  Topology  System-on-chip  Solid State Circuits  Inductors  
34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC Conference paper
Yuan, Yiyang, Yang, Yiming, Wang, Xinghua, Li, Xiaoran, Ma, Cailian, Chen, Qirui, Tang, Meini, Wei, Xi, Hou, Zhixian, Zhu, Jialiang, Wu, Hao, Ren, Qirui, Xing, Guozhong, Mak, Pui In, Zhang, Feng. 34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 576-578.
Authors:  Yuan, Yiyang;  Yang, Yiming;  Wang, Xinghua;  Li, Xiaoran;  Ma, Cailian; et al.
Favorite | TC[Scopus]:2 | Submit date：2024/05/16
Training  Random Access Memory  Throughput  Common Information Model (Computing)  System-on-chip  Solid State Circuits  Complexity Theory  
CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization Journal article
Fu, Yuzhao, Li, Jixuan, Yu, Wei Han, Un, Ka Fai, Chan, Chi Hang, Zhu, Yan, Martins, Rui P., Mak, Pui In. CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Fu, Yuzhao;  Li, Jixuan;  Yu, Wei Han;  Un, Ka Fai;  Chan, Chi Hang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/07/04
Capacitance Lookup Table (Clut)  Circuits  Common Information Model (Computing)  Compute-in-memory (Cim)  Energy Efficiency  High Energy Efficiency  In-memory Computing  Indexes  Nonuniform Quantization (Nuq)  Table Lookup  Thermometers  Weight Updating  
Camera-aware Differentiated Clustering with Focal Contrastive Learning for Unsupervised Vehicle Re-Identification Journal article
Qiu, Mingkai, Lu, Yuhuan, Li, Xiying, Lu, Qiang. Camera-aware Differentiated Clustering with Focal Contrastive Learning for Unsupervised Vehicle Re-Identification[J]. IEEE Transactions on Circuits and Systems for Video Technology, 2024.
Authors:  Qiu, Mingkai;  Lu, Yuhuan;  Li, Xiying;  Lu, Qiang
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:8.3/7.1 | Submit date：2024/06/05
Cameras  Circuits And Systems  Differentiated Clustering  Focal Contrastive Learning  Intelligent Systems  Noise  Task Analysis  Training  Unsupervised Learning  Unsupervised Learning  Vehicle Re-identification  
A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity Journal article
Wu, Hao, Chen, Yong, Yuan, Yiyang, Yue, Jinshan, Wang, Xinghua, Li, Xiaoran, Zhang, Feng. A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Wu, Hao;  Chen, Yong;  Yuan, Yiyang;  Yue, Jinshan;  Wang, Xinghua; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/07/04
Accuracy  Artificial Intelligence  Artificial Intelligence (Ai)  Circuits  Cmos  Computing-in-memory (Cim)  Energy Efficiency  Energy Efficiency  Look-up Table (Lut)  Multiply-accumulation (Mac)  Neural Network (Nn)  Power Demand  Radix16  Table Lookup  Throughput  Unstructured Sparsity  Winograd Convolution  
3.3 A 0.5V 6.14μW Trimming-Free Single-XO Dual-Output Frequency Reference with [5.1nJ, 120μs] XO Startup and [8.1nJ, 200μs] Successive-Approximation-Based RTC Calibration Conference paper
Luo, Rui, Lei, Ka Meng, Martins, Rui P., Mak, Pui In. 3.3 A 0.5V 6.14μW Trimming-Free Single-XO Dual-Output Frequency Reference with [5.1nJ, 120μs] XO Startup and [8.1nJ, 200μs] Successive-Approximation-Based RTC Calibration[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 58-60.
Authors:  Luo, Rui;  Lei, Ka Meng;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[Scopus]:0 | Submit date：2024/05/16
Training  Costs  Real-time Systems  Calibration  Solid State Circuits  Quartz Crystals  Oscillators  
17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM Conference paper
Tan, Fei, Yu, Wei Han, Lin, Jinhai, Un, Ka Fai, Martins, Rui P., Mak, Pui In. 17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 330-332.
Authors:  Tan, Fei;  Yu, Wei Han;  Lin, Jinhai;  Un, Ka Fai;  Martins, Rui P.; et al.
Favorite | TC[Scopus]:1 | Submit date：2024/05/16
Computational Modeling  User Experience  Hardware  Computational Efficiency  Solid State Circuits