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An 8-b 400-ms/s 2-b-per-cycle sar adc with resistive dac Journal article
Hegong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti. An 8-b 400-ms/s 2-b-per-cycle sar adc with resistive dac[J]. IEEE Journal of Solid-State Circuits, 2012, 47(11), 2763-2772.
Authors:  Hegong Wei;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:68 TC[Scopus]:82  IF:4.6/5.6 | Submit date：2018/10/30
2-b-per-cycle (2 B/c)  Analog-to-digital Converter (Adc)  Resistive Dac  Successive Approximation Register (Sar)