An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integratedcircuit implementation, the proposed SAR ADC achievesrapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input. The measured FOM is 73 fJ/conversion-step at 400MS/s from 1.2-V supply and 42 fJ/conversion-step at 250MS/s from a 1-V supply. The active area with the digital calibration is 0.028 mm .© 1966-2012 IEEE.