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Correction to: E3 ubiquitin ligase UBR5 modulates circadian rhythm by facilitating the ubiquitination and degradation of the key clock transcription factor BMAL1 (Acta Pharmacologica Sinica, (2024), 10.1038/s41401-024-01290-z) Other
2024-12-01
Authors:  Duan, Chun Yan;  Li, Yue;  Zhi, Hao Yu;  Tian, Yao;  Huang, Zheng Yun; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/07/04
An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
Cao, Rujian, Zhao, Zhongyu, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(11), 4688-4692.
Authors:  Cao, Rujian;  Zhao, Zhongyu;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/10/10
Sparse Matrices  Computational Modeling  Transformers  Hardware  Energy Efficiency  Circuits  Throughput  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Sparsity  Transformer  
An 80W Single-Inductor DC-DC Architecture for Simultaneous Flash Charging and Dual-Output PoL Supply with 92.1% Peak Efficiency from 15V-to-28V Input to 12.6V/3.3V/1V Outputs Using 1.3mm3Inductor Conference paper
Zhang, Xiongjie, Zhao, Anyang, Li, Xinman, Jiang, Yang, Martins, Rui P., Mak, Pui In. An 80W Single-Inductor DC-DC Architecture for Simultaneous Flash Charging and Dual-Output PoL Supply with 92.1% Peak Efficiency from 15V-to-28V Input to 12.6V/3.3V/1V Outputs Using 1.3mm3Inductor[C]:IEEE Computer Society, 2024, 61-64.
Authors:  Zhang, Xiongjie;  Zhao, Anyang;  Li, Xinman;  Jiang, Yang;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/12/05
Dc-dc  Flash-charger  Integrated Gate Driver  Power Delivery  Single-inductor Multiple-output  
A Cross-Coupled Hybrid Switched-Capacitor Buck Converter With Extended Conversion Range and Enhanced DCR Loss Reduction Journal article
Qiaobo Ma, Huihua Li, Xiongjie Zhan, Anyang Zhao, Yang Jiang, Man-Kay Law, Rui P. Martins, Pui-In Mak. A Cross-Coupled Hybrid Switched-Capacitor Buck Converter With Extended Conversion Range and Enhanced DCR Loss Reduction[J]. IEEE Journal of Solid-State Circuits, 2024, 59(10), 3192-3203.
Authors:  Qiaobo Ma;  Huihua Li;  Xiongjie Zhan;  Anyang Zhao;  Yang Jiang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/08/29
Cross-coupled  Dc Resistance (Dcr)  Hybrid Switched-capacitor (Sc)  Inductor Current Reduction  Level Shifter  
Comprehensive classification of TP53 somatic missense variants based on their impact on p53 structural stability Journal article
Benjamin Tam, Philip Naderev P. Lagniton, Mariano da Luz, Bojin Zhao, Siddharth Sinha, Chon Lok Lei, San Ming Wang. Comprehensive classification of TP53 somatic missense variants based on their impact on p53 structural stability[J]. Briefings in Bioinformatics, 2024, 25(5), bbae400.
Authors:  Benjamin Tam;  Philip Naderev P. Lagniton;  Mariano da Luz;  Bojin Zhao;  Siddharth Sinha; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:6.8/7.9 | Submit date：2024/08/07
Ramachandran Plot  Molecular Dynamics Simulations  Tp53  Somatic Missense Variants  
A Reconfigurable Floating-Point Compute-In-Memory With Analog Exponent Pre-Processes Journal article
He, Pengyu, Zhao, Yuanzhe, Xie, Heng, Wang, Yang, Yin, Shouyi, Li, Li, Zhu, Yan, Martins, Rui P., Chan, Chi Hang, Zhang, Minglei. A Reconfigurable Floating-Point Compute-In-Memory With Analog Exponent Pre-Processes[J]. IEEE Solid-State Circuits Letters, 2024, 7, 271-274.
Authors:  He, Pengyu;  Zhao, Yuanzhe;  Xie, Heng;  Wang, Yang;  Yin, Shouyi; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/10/10
Compute-in-memory Macro(Cim)  Exponent Pre-process  Floating-point(Fp)  Reconfigurable  Segmented Computation  
An FPGA-Based Transformer Accelerator with Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
CAO RUJIAN, ZHAO ZHONGYU, UN KA FAI, YU WEI HAN, RUI P. MARTINS, MAK PUI IN. An FPGA-Based Transformer Accelerator with Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024.
Authors:  CAO RUJIAN;  ZHAO ZHONGYU;  UN KA FAI;  YU WEI HAN;  RUI P. MARTINS; et al.
Favorite |  | Submit date：2024/08/29
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
ZHANG RAN, UN KA FAI, GUO MINGQIANG, QI LIANG, XU DENGKE, ZHAO WEIBING, RUI P. MARTINS, FRANCO MALOBERTI, SIN SAI WENG. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  ZHANG RAN;  UN KA FAI;  GUO MINGQIANG;  QI LIANG;  XU DENGKE; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/08/19
Machine Learning  Edge Computation  Computing-in-memory  Delta-sigma Converter  Floating Inverter Amplifier  
A 63ns Flipping Time, 93.6% Voltage Flipping Efficiency Auto-Calibrated Ultrasonic Energy Harvesting Interface from-25 to 85°C Conference paper
Zhao, Guangshu, Xie, Chao, Wang, Chenxi, Jiang, Yang, Zhang, Milin, Mak, Pui In, Martins, Rui P., Law, Man Kay. A 63ns Flipping Time, 93.6% Voltage Flipping Efficiency Auto-Calibrated Ultrasonic Energy Harvesting Interface from-25 to 85°C[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Zhao, Guangshu;  Xie, Chao;  Wang, Chenxi;  Jiang, Yang;  Zhang, Milin; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2024/06/05
The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs Conference paper
Chan, Chi Hana, Zhang, Minglei, Cao, Yuefena, Zhao, Honazhi, Martins, Rui P., Zhu, Yan. The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 28-1.
Authors:  Chan, Chi Hana;  Zhang, Minglei;  Cao, Yuefena;  Zhao, Honazhi;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/06/05
Technological Innovation  Quantization (Signal)  Power Demand  Energy Resolution  Reliability Engineering  Energy Efficiency  Trajectory  Time-domain Analysis  Task Analysis  Signal Resolution