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A 5.99-GHz VCO with Wideband-Differential-Mode Second Harmonic Resonance Achieving - 138.9 dBc/Hz Phase Noise at an Offset of 10 MHz Journal article
Yang, Chaowei, Chen, Yong, Huang, Yunbo, Martins, Rui P., Mak, Pui In. A 5.99-GHz VCO with Wideband-Differential-Mode Second Harmonic Resonance Achieving - 138.9 dBc/Hz Phase Noise at an Offset of 10 MHz[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(11), 1267-1270.
Authors:  Yang, Chaowei;  Chen, Yong;  Huang, Yunbo;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:0/0 | Submit date：2024/11/05
1/f3 Pn Corner  Cmos  Figure-of-merit (Fom)  Impulse Sensitivity Function (Isf)  Phase Noise (Pn)  Voltage-controlled Oscillator (Vco)  Wideband-harmonic Shaping  
A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
7.4 A 0.027mm25.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrmsJitter and -74.2dBc Reference Spur Conference paper
Huang, Yunbo, Chen, Yong, Yang, Zunsong, Martins, Rui P., Mak, Pui In. 7.4 A 0.027mm25.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrmsJitter and -74.2dBc Reference Spur[C]:IEEE, 2024, 130-132.
Authors:  Huang, Yunbo;  Chen, Yong;  Yang, Zunsong;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[Scopus]:1 | Submit date：2024/05/16
A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur Conference paper
Chen, Tianle, Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Zheng, Xuqiang, Guo, Xuan, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Chen, Tianle;  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Meng, Xianghe; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/10/10
A 28 nm 368 fJ/cycle, 0.43%/V Supply Sensitivity, FLL based RC Oscillator Featuring Positive TC Only Resistors and ΣM Based Trimming Journal article
Huang,Yunbo, Chen,Yong, Yang,Kaiyuan, Crovetti,Paolo, Mak,Pui In, Martins,Rui P.. A 28 nm 368 fJ/cycle, 0.43%/V Supply Sensitivity, FLL based RC Oscillator Featuring Positive TC Only Resistors and ΣM Based Trimming[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(11), 3950-3954.
Authors:  Huang,Yunbo;  Chen,Yong;  Yang,Kaiyuan;  Crovetti,Paolo;  Mak,Pui In; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2023/08/03
Clocks  Cmos  Delta-sigma-modulator  Energy Efficiency  Frequency Inaccuracy  Frequency-locked-loop (Fll)  Generators  Oscillators  Rc Oscillator  Resistance  Resistors  Switched-capacitor Resistor  Switches  Temperature Coefficients  Voltage-controlled Oscillators  
A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output Conference paper
Huang, Yunbo, Chen, Yong, Yang, Chaowei, Mak, Pui In, Martins, Rui P.. A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output[C], USA:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Huang, Yunbo;  Chen, Yong;  Yang, Chaowei;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/02/23
1/f3pn Corner  Cmos  Common-mode (Cm) Resonance  Figure-of-merit (Fom)  Flicker (1/f) Noise  Impulse Sensitivity Function (Isf)  Noise Transfer  Phase Noise (Pn)  Quality Factor  Thermal Noise  Tuning Range (Tr)  Voltage-controlled Oscillator (Vco)  
A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur Journal article
Huang, Yunbo, Chen, Yong, Zhao, Bo, Mak, Pui In, Martins, Rui P.. A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70(4), 1463-1475.
Authors:  Huang, Yunbo;  Chen, Yong;  Zhao, Bo;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:11  IF:5.2/4.5 | Submit date：2023/05/02
Cmos  Type-i Sampling Phase-locked Loop (S-pll)  Voltage-controlled Oscillator (Vco)  Reference (Ref) Feedthrough Suppression  Figure-of-merit (Fom)  Phase-detection Gain (Kpd)  Sampling Phase Detector (S-pd)  
Universal Stability Criterion for Type-I Sampling Phase-Locked Loops Journal article
Huang, Yunbo, Chen, Yong, Mak, Pui In, Martins, Rui P.. Universal Stability Criterion for Type-I Sampling Phase-Locked Loops[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(4), 1351-1355.
Authors:  Huang, Yunbo;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:4.0/3.7 | Submit date：2023/05/02
Given Phase Margin (Pm)  Linear Time-variant (Ltv) Mode  Sampling Phase-locked Loop (S-pll)  Sub-sampling Pll (ss-Pll)  Type-i  Voltage-controlled Oscillator (Vco)  
8.4 An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz FoMT Conference paper
Hao Guo, Yong Chen, Yunbo Huang, Pui In Mak, Rui P. Martins. 8.4 An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz FoMT[C]:Institute of Electrical and Electronics Engineers Inc., 2023, 152-154.
Authors:  Hao Guo;  Yong Chen;  Yunbo Huang;  Pui In Mak;  Rui P. Martins
Favorite | TC[Scopus]:8 | Submit date：2023/08/03
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur Journal article
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui P. Martins. A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 188-198.
Authors:  Yunbo Huang;  Yong Chen;  Bo Zhao;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:4 TC[Scopus]:9  IF:2.8/2.8 | Submit date：2023/02/22
Cmos  Figure-of-merit (Fom)  Harmonic-rich Voltage-controlled Oscillator (Vco)  Integrated Jitter, Phase-detection Gain (Kpd)  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  Reference (Ref) Feedthrough Suppression  Type-i  Type-ii