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A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing Journal article
Guo Mingqiang, Qi Liang, Zhao Weibing, Xiao Gangjun, Rui P. Martins, Sin Sai-Weng. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4767-4780.
Authors:  Guo Mingqiang;  Qi Liang;  Zhao Weibing;  Xiao Gangjun;  Rui P. Martins; et al.
Adobe PDF | Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2023/08/21
Analog-to-digital Converter (Adc)  Successive Approximation Register (Sar)  Power-delay-optimized  Unbalanced N/p-mos Sizing Buffers  Monotonic Switching  
A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing Conference paper
Guo, Mingqiang, Sin, Sai Weng, Qi, Liang, Xiao, Gangjun, Martins, Rui P.. A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing[C], 2022.
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xiao, Gangjun;  Martins, Rui P.
Adobe PDF | Favorite | TC[Scopus]:7 | Submit date：2022/08/05