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Histogram-based ratio mismatch calibration for bridge-DAC in 12-bit 120 MS/s SAR ADC Journal article
Yan Zhu, Chi-Hang Chan, Si-Seng Wong, U Seng-Pan, Rui Paulo Martins. Histogram-based ratio mismatch calibration for bridge-DAC in 12-bit 120 MS/s SAR ADC[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(3), 1203-1207.
Authors:  Yan Zhu;  Chi-Hang Chan;  Si-Seng Wong;  U Seng-Pan;  Rui Paulo Martins
Favorite | TC[WOS]:29 TC[Scopus]:32 | Submit date：2019/02/11
Bridge Dac  Linearity Calibration  Sar Adc  
A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC Journal article
Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC[J]. IEEE Journal of Solid-State Circuits, 2013, 48(8), 1783-1794.
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:27 TC[Scopus]:35  IF:4.6/5.6 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Sar Adc  Time-interleaved  Two-step Adc  
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC Conference paper
Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC[C], 2012.
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:0 TC[Scopus]:10 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Time-interleaved  Sar Adc  Two-step Adc