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A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Wng Sin, Seng-Pan U, Rui Paulo Martins. A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, 64(7), 1684-1695.
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Wng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:23 TC[Scopus]:30 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching Journal article
Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Wng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins. Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25(3), 1168-1172.
Authors:  Dezhi Xing;  Yan Zhu;  Chi-Hang Chan;  Sai-Wng Sin;  Fan Ye; et al.
Favorite | TC[WOS]:14 TC[Scopus]:17 | Submit date：2019/02/11
Common Mode Variation  Partial Vcm-based Switching  Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)