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A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM Conference paper
Ren, Hongyu, Huang, Yunbo, Yang, Zunsong, Chen, Tianle, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Li, Zhongmao, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM[C]:IEEE Computer Society, 2024, 113-116.
Authors:  Ren, Hongyu;  Huang, Yunbo;  Yang, Zunsong;  Chen, Tianle;  Meng, Xianghe; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/12/05
Clock Generator  Frequency Synthesizer  Low Jitter  Low Power  Low Spur  Phase-locked Loop (Pll)  Reference Sampling  Type-ii