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THE STATE KEY LA... [2]
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CHEN YONG [2]
MAK PUI IN [1]
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A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector
Conference paper
Ge, Xinyi, Chen, Yong, Wang, Lin, Qi, Nan, Mak, Pui In, Martins, Rui P.. A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2022.
Authors:
Ge, Xinyi
;
Chen, Yong
;
Wang, Lin
;
Qi, Nan
;
Mak, Pui In
; et al.
Favorite
|
TC[WOS]:
4
TC[Scopus]:
5
|
Submit date:2023/01/30
Bang-bang Phase Detector (Bbpd)
Charge Steering
Clock And Data Recovery (Cdr)
Cmos
Half Rate
Non- Return-to-zero (Nrz)
Quadrature Voltage-controlled Oscillator (Qvco)
Return-to-zero (Rz)
Rz-to-nrz Converter
Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter
Journal article
Ge,Xinyi, Chen,Yong, Zhao,Xiaoteng, Mak,Pui In, Martins,Rui P.. Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(10), 2223-2236.
Authors:
Ge,Xinyi
;
Chen,Yong
;
Zhao,Xiaoteng
;
Mak,Pui In
;
Martins,Rui P.
Favorite
|
TC[WOS]:
19
TC[Scopus]:
19
IF:
2.8
/
2.8
|
Submit date:2021/03/09
Bang-bang Clock And Data Recovery (Bbcdr)
Bang-bang Phase Detector (Bbpd)
Binary
Fourier Series
Jitter Generation (Jgen)
Jitter Tolerance (Jtol)
Jitter Transfer Function (Jtf)
Linear Phase Detector
Loop Filter (Lf)
Sinking Area