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A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:0/0 | Submit date:2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Power  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Type-i  
A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM Conference paper
Ren, Hongyu, Huang, Yunbo, Yang, Zunsong, Chen, Tianle, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Li, Zhongmao, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM[C]:IEEE Computer Society, 2024, 113-116.
Authors:  Ren, Hongyu;  Huang, Yunbo;  Yang, Zunsong;  Chen, Tianle;  Meng, Xianghe; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date:2024/12/05
Clock Generator  Frequency Synthesizer  Low Jitter  Low Power  Low Spur  Phase-locked Loop (Pll)  Reference Sampling  Type-ii  
Operational Research: methods and applications Review article
2024
Authors:  Petropoulos, Fotios;  Laporte, Gilbert;  Aktas, Emel;  Alumur, Sibel A.;  Archetti, Claudia; et al.
Favorite | TC[WOS]:18 TC[Scopus]:20  IF:2.7/3.0 | Submit date:2024/05/16
Decision Making  Encyclopedia  Models  Optimisation  Practice  Principles  Programming  Review  Simulation  Systems  Theory  
A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur Journal article
Huang, Yunbo, Chen, Yong, Zhao, Bo, Mak, Pui In, Martins, Rui P.. A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70(4), 1463-1475.
Authors:  Huang, Yunbo;  Chen, Yong;  Zhao, Bo;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:7 TC[Scopus]:11  IF:5.2/4.5 | Submit date:2023/05/02
Cmos  Type-i Sampling Phase-locked Loop (S-pll)  Voltage-controlled Oscillator (Vco)  Reference (Ref) Feedthrough Suppression  Figure-of-merit (Fom)  Phase-detection Gain (Kpd)  Sampling Phase Detector (S-pd)  
A 72-Channel Resistive-and-Capacitive Sensor Interface Achieving 0.74 μ W/ Channel and 0.038 mm2/ Channel by Noise-Orthogonalizing and Pad-Sharing Techniques Conference paper
Feng,Xiangdong, Luo,Yuxuan, Cai,Tianyi, Xuan,Yangfan, Zhang,Yunshan, Shen,Yili, Yang,Changgui, Xiao,Qijing, Chen,Yong, Zhao,Bo. A 72-Channel Resistive-and-Capacitive Sensor Interface Achieving 0.74 μ W/ Channel and 0.038 mm2/ Channel by Noise-Orthogonalizing and Pad-Sharing Techniques[C]:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Feng,Xiangdong;  Luo,Yuxuan;  Cai,Tianyi;  Xuan,Yangfan;  Zhang,Yunshan; et al.
Favorite | TC[Scopus]:4 | Submit date:2023/08/03
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur Journal article
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui P. Martins. A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 188-198.
Authors:  Yunbo Huang;  Yong Chen;  Bo Zhao;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:5 TC[Scopus]:10  IF:2.8/2.8 | Submit date:2023/02/22
Cmos  Figure-of-merit (Fom)  Harmonic-rich Voltage-controlled Oscillator (Vco)  Integrated Jitter, Phase-detection Gain (Kpd)  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  Reference (Ref) Feedthrough Suppression  Type-i  Type-ii  
A Crystal-Less Clock Generation Technique for Battery-Free Wireless Systems Journal article
Chang, Ziyi, Zhang, Yunshan, Yang, Changgui, Luo, Yuxuan, Du, Sijun, Chen, Yong, Zhao, Bo. A Crystal-Less Clock Generation Technique for Battery-Free Wireless Systems[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(12), 4981-4992.
Authors:  Chang, Ziyi;  Zhang, Yunshan;  Yang, Changgui;  Luo, Yuxuan;  Du, Sijun; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:5.2/4.5 | Submit date:2023/01/30
Battery-free  Clock Generator  Wireless Power Transfer (Wpt)  Injection Locking  Inter-modulation  
A Square-Wave Stimulated DNA Analyzer Chip Featuring 120μW Power Consumption and Simultaneous Dual-Frequency Detection Journal article
Feng, Xiangdong, Zhang, Yunshan, Xuan, Yangfan, Li, Zhuhao, Yang, Changgui, Xie, Xin, Luo, Yuxuan, Zhao, Xiangwei, Chen, Yong, Zhao, Bo. A Square-Wave Stimulated DNA Analyzer Chip Featuring 120μW Power Consumption and Simultaneous Dual-Frequency Detection[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69(10), 4093-4097.
Authors:  Feng, Xiangdong;  Zhang, Yunshan;  Xuan, Yangfan;  Li, Zhuhao;  Yang, Changgui; et al.
Favorite | TC[WOS]:0 TC[Scopus]:3  IF:4.0/3.7 | Submit date:2022/08/05
Dna  Dna Analyzer  Harmonic  Harmonic Analysis  Impedance  Impedance Spectroscopy  Low Power  Power Harmonic Filters  Semiconductor Device Measurement  Spectroscopy  Stimulation  Testing  
A Power-Harvesting CGM Chiplet Featuring Silicon-Based Enzymatic Glucose Sensor Conference paper
Wang, Ting Hsun, Li, Zhuhao, Liang, Bo, Cai, Yu, Wang, Zhiyu, Yang, Changgui, Luo, Yuxuan, Sun, Jiabao, Ye, Xuesong, Chen, Yong, Zhao, Bo. A Power-Harvesting CGM Chiplet Featuring Silicon-Based Enzymatic Glucose Sensor[C]:Institute of Electrical and Electronics Engineers Inc., 2022, 4626-4630.
Authors:  Wang, Ting Hsun;  Li, Zhuhao;  Liang, Bo;  Cai, Yu;  Wang, Zhiyu; et al.
Favorite | TC[Scopus]:5 | Submit date:2023/01/30
A 2m-Range 711uW Body Channel Communication Transceiver Featuring Dynamically-Sampling Bias-Free Interface Front End Conference paper
Gu, Guanjie, Yang, Changgui, Li, Zhuhao, Feng, Xiangdong, Chang, Ziyi, Wang, Ting Hsun, Zhang, Yunshan, Luo, Yuxuan, Zhang, Hong, Wang, Ping, Du, Sijun, Chen, Yong, Zhao, Bo. A 2m-Range 711uW Body Channel Communication Transceiver Featuring Dynamically-Sampling Bias-Free Interface Front End[C]:IEEE, 2022, 10-12.
Authors:  Gu, Guanjie;  Yang, Changgui;  Li, Zhuhao;  Feng, Xiangdong;  Chang, Ziyi; et al.
Favorite | TC[Scopus]:1 | Submit date:2023/03/06