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FPGA based Implied Volatility Calculation with Multi-section Method
Wang, Su1; Huan, Hongxin2; Wong, Seng Fat3; Yen, Joseph3
2022-07
Conference Name2022 IEEE 20th International Conference on Industrial Informatics (INDIN)
Source PublicationIEEE International Conference on Industrial Informatics INDIN
Volume2022-July
Pages507-514
Conference Date25/07/2022-28/07/2022
Conference PlacePerth
CountryAustralia
Author of SourceInstitute of Electrical and Electronics Engineers Inc.
Publication PlaceUSA
PublisherIEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Abstract

The calculation of implied volatility is important in the financial industry, as it is frequently used for hedging and trading strategies. In addition, there is a great need for a low-latency yet precise method to calculate. In this paper, we propose a calculation framework that utilizes parallelism for lower latency as a whole. It is an extension of the Bi-section Method that we call the Multi-section method. It allows traders to utilize FPGA, GPU, and other hardware accelerators to quickly compute the computation of IV in a parallel manner. In addition, to solve the difficulty of complex operators, we also developed a hybrid computing architecture that mixes FPGAs, CPUs, and GPUs to offload difficult tasks unsuitable for FPGAs. Finally, our algorithm is implemented and tested on both GPUs and FPGAs. Using data collected from the S&P 500 index, we can validate that they are at least 4 to 5 times faster than traditional methods. Using this framework, we can predict the market’s potential direction in a faster way.

KeywordOption Pricing Implied Volatility Black-scholes Method Fpga Multi-section Method Heterogeneous Computing
DOI10.1109/INDIN51773.2022.9976086
Indexed ByCPCI-S
WOS IDWOS:000907121600080
Scopus ID2-s2.0-85145768635
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Citation statistics
Document TypeConference paper
CollectionDEPARTMENT OF FINANCE AND BUSINESS ECONOMICS
Faculty of Science and Technology
DEPARTMENT OF ELECTROMECHANICAL ENGINEERING
DEPARTMENT OF COMPUTER AND INFORMATION SCIENCE
Affiliation1.Dept. of Finance and Business Economics University of Macau Macao SAR, China
2.Dept. of Computer Science University of Macau Macao SAR, China
3.Dept. of Electo-Mechanical Engineering University of Macau Macao SAR, China
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Wang, Su,Huan, Hongxin,Wong, Seng Fat,et al. FPGA based Implied Volatility Calculation with Multi-section Method[C]. Institute of Electrical and Electronics Engineers Inc., USA:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2022, 507-514.
APA Wang, Su., Huan, Hongxin., Wong, Seng Fat., & Yen, Joseph (2022). FPGA based Implied Volatility Calculation with Multi-section Method. IEEE International Conference on Industrial Informatics INDIN, 2022-July, 507-514.
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