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A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration Journal article
Wei, Lai, Zheng, Zihao, Markulic, Nereo, Lagos, Jorge, Martens, Ewout, Martins, Rui Paulo, Zhu, Yan, Craninckx, Jan, Chan, Chi Hang. A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4679-4691.
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout; et al.
Favorite | TC[WOS]:3 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2024/02/23
Analog-to-digital Converter  Cmos Analog Integrated Circuits  Distortion  Input Buffer  Split-adc-like Calibration  
A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer Journal article
Xu, Zhuofan, Hu, Biao, Wu, Tianxiang, Yao, Yuting, Chen, Yong, Ren, Junyan, Ma, Shunli. A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer[J]. Electronics (Switzerland), 2022, 11(12).
Authors:  Xu, Zhuofan;  Hu, Biao;  Wu, Tianxiang;  Yao, Yuting;  Chen, Yong; et al.
Favorite | TC[WOS]:7 TC[Scopus]:10  IF:2.6/2.6 | Submit date：2022/08/02
Split Cdac  Asynchronous Sar Adc  Input Pga  Rv-buffer  
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations Journal article
Zhang, Yanbo, Zhang, Jin, Liu, Shubin, Ding, Ruixue, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations[J]. IEEE Journal of Solid-State Circuits, 2022, 57(3), 745-756.
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Ding, Ruixue;  Zhu, Yan; et al.
Favorite | TC[WOS]:7 TC[Scopus]:10  IF:4.6/5.6 | Submit date：2022/03/28
Analog-to-digital Converter (Adc)  Inter-stage Gain And Offset Calibrations  Noise-shaping (Ns)  Split Adc  Successive Approximation Register (Sar)-assisted Pipeline  
An Auxiliary-Channel-Sharing Background Distortion and Gain CalibrationAchieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC Conference paper
Wei, L., Zheng, Z., Markulic, N., Lagos, J., Martens, E., Zhu, Y., Chan, C. H., Craninckx, J., Martins, R. P.. An Auxiliary-Channel-Sharing Background Distortion and Gain CalibrationAchieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC[C], 2021.
Authors:  Wei, L.;  Zheng, Z.;  Markulic, N.;  Lagos, J.;  Martens, E.; et al.
Favorite |  | Submit date：2022/01/25
Background Calibration  Nonlinearity  Pipelined Adc  Split-sar Adc  
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC Conference paper
Wei, Lai, Zheng, Zihao, Markulic, Nereo, Lagos, Jorge, Martens, Ewout, Zhu, Yan, Chan, Chi Hang, Craninckx, Jan, Martins, Rui Paulo. An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC[C], 2021.
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout; et al.
Favorite | TC[Scopus]:3 | Submit date：2021/09/20
Background Calibration  Nonlinearity  Pipelined Adc  Split-sar Adc  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
Guo,Mingqiang, Mao,Jiaji, Sin,Sai Weng, Wei,Hegong, Martins,Rui P.. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits, 2020, 55(3), 693-705.
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Adobe PDF | Favorite | TC[WOS]:51 TC[Scopus]:54  IF:4.6/5.6 | Submit date：2021/03/04
Analog-to-digital Converter (Adc)  Digital Background Calibration  Split Adc  Time-interleaved (Ti) Adc  Timing-skew Mismatch  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration Journal article
Guo Mingqiang, Mao Jiaji, Sin Sai-Weng, Wei Hegong, Rui P. Martins. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits, 2020, 55(3), 693-705.
Authors:  Guo Mingqiang;  Mao Jiaji;  Sin Sai-Weng;  Wei Hegong;  Rui P. Martins
Adobe PDF | Favorite | TC[WOS]:51 TC[Scopus]:54  IF:4.6/5.6 | Submit date：2022/08/20
Analog-to-Digital Converter (Adc), Digital Background CalibraTion, Split Adc, Time-interleaved (Ti) Adc, Timing-skew Mismatch  
A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Guo, M., Mao, J., Sin, S. W., Wei, H., Martins, R. P.. A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration[C], 2019.
Authors:  Guo, M.;  Mao, J.;  Sin, S. W.;  Wei, H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
SAR analog-to-digital converter (ADC)  time-interleaved (TI) ADC  timing-skew calibration  split ADC  background mismatch calibration  
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Guo,Mingqiang, Mao,Jiaji, Sin,Sai Weng, Wei,Hegong, Martins,R. P.. A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2019, 8780222.
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
Adobe PDF | Favorite | TC[WOS]:13 TC[Scopus]:9 | Submit date：2021/03/09
Sar Analog-to-digital Converter (Adc)  Time-interleaved (Ti) Adc  Timing-skew Calibration  Split Adc  Background Mismatch Calibration  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
Liu J., Chan C.-H., Sin S.-W., Seng-Pan U., Martins R.P.. Accuracy-enhanced variance-based time-skew calibration using SAR as window detector[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(2), 481-485.
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:2.8/2.8 | Submit date：2019/02/13
Bandwidth Mismatches  Split-digital To Analog Converter (Dac)  Successive-approximation-register (Sar) Analog-to-digital Converter (Adc)  Time-interleaved (Ti)  Variance Based  Window Detector (Wd)