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A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC Journal article
Zhao, Hongzhi, Zhang, Minglei, Zhu,Yan, Martins, R. P., Chan,Chi Hang. A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3586-3597.
Authors:  Zhao, Hongzhi;  Zhang, Minglei;  Zhu,Yan;  Martins, R. P.;  Chan,Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2023/08/29
Analog-to-digital Converter (Adc)  Multi-bit/cycle Successive-approximation Register (Sar) Adc  Time-domain Quantization  Voltage-to-time (V2t) Buffer  Linearization  
An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC Conference paper
Zeng, Yi, Chan, Chi Hang, Zhu, Yan, Martins, Rui P.. An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC[C], 2022, 2660-2664.
Authors:  Zeng, Yi;  Chan, Chi Hang;  Zhu, Yan;  Martins, Rui P.
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2023/01/30
Analog-to-digital Converter (Adc)  Flipped Voltage Follower (Fvf)  Reference Buffer  Successive Approximation Register (Sar)  
A Slew Rate Variation Compensated 2 x VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method Journal article
Lee, Tzung-Je, Tsai, Tsung-Yi, Lin, Wei, Chio, U-Fat, Wang, Chua-Chin. A Slew Rate Variation Compensated 2 x VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2019, 66(1), 116-120.
Authors:  Lee, Tzung-Je;  Tsai, Tsung-Yi;  Lin, Wei;  Chio, U-Fat;  Wang, Chua-Chin
Favorite | TC[WOS]:13 TC[Scopus]:14  IF:4.0/3.7 | Submit date：2019/01/17
I/o Buffer  Mixed-voltage Tolerant  Pvt Variation  Leakage  Slew Rate Compensation  
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer Journal article
Lee, Tzung-Je, Tsai, Tsung-Yi, Lin, Wei, Chio, U-Fat, Wang, Chua-Chin. A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25(11), 3166-3174.
Authors:  Lee, Tzung-Je;  Tsai, Tsung-Yi;  Lin, Wei;  Chio, U-Fat;  Wang, Chua-Chin
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:2.8/2.8 | Submit date：2018/10/30
Dynamic Leakage Reduction  I/o Buffer  Mixed-voltage Tolerant  Process-voltage-temperature (Pvt) Variation  Slew Rate Compensation  
A 0.137mm29 GHz hybrid class-B/C QVCO with output buffering in 65nm CMOS Journal article
Md. Tawfiq Amin, Pui-In Mak, Rui P. Martins. A 0.137mm29 GHz hybrid class-B/C QVCO with output buffering in 65nm CMOS[J]. IEEE Microwave and Wireless Components Letters, 2014, 24(10), 716-718.
Authors:  Md. Tawfiq Amin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:4 TC[Scopus]:5  IF:2.9/3.0 | Submit date：2019/02/11
Buffer  Cmos  Class-b  Class-c  Phase Noise  Qu!adrature Voltage-controlled Oscillator (Qvco)  
On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC Conference paper
Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R. P. Martins. On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC[C], 2005, 276-280.
Authors:  Weng-Ieng Mok;  Pui-In Mak;  Seng-Pan U;  R. P. Martins
Favorite |  | Submit date：2019/02/28
High-speed  Pipelined Analog-to-digital Converter  Reference Voltage  Voltage Buffer