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Energy Optimized Subthreshold VLSI Logic Family with Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques
Journal article
Ming-Zhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang-I Vai, Sio-Hang Pun, Rui P. Martins. Energy Optimized Subthreshold VLSI Logic Family with Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(12), 3119-3123.
Authors:
Ming-Zhong Li
;
Chio-In Ieong
;
Man-Kay Law
;
Pui-In Mak
;
Mang-I Vai
; et al.
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Submit date：2019/02/11
Cmos
Device Sizing
Electrocardiography (Ecg)
Finite Impulse Response (Fir) Filter
Inverse Narrow Width (Inw)
Logical Effort
Process-voltage-temperature (Pvt) Variations
Subthreshold Standard Logic Library
Ultralow Energy
Ultralow Voltage.
