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A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator Journal article
Zhang, Hongshuai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3565-3575.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:4.6/5.6 | Submit date：2024/01/02
Analog-to-digital Converter (Adc)  Auxiliary Noise Shaping (Ns) Successive-approximation Register (Sar) Adc  Capacitor Stacking  Data-weighted Averaging And detect-And-skip (Dwa And Das)  Differential Sampling  Energy Efficient  Error SupprEssion (Es) And Reconstruction  Gain Error Shaping (Ges)  Partial Time Interleaving  Passive Ns  Pipelined Sar  Quantization Predication Unrolled  Two-step Floating Inverter Amplifier (Fia)  
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques Journal article
Zhang,Minglei, Chan,Chi Hang, Zhu,Yan, Martins,Rui P.. A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques[J]. IEEE Journal of Solid-State Circuits, 2019, 54(12), 3396-3409.
Authors:  Zhang,Minglei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:27 TC[Scopus]:41  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Low Power Supply  Process  Voltage  And Temperature (Pvt) Robustness  Successive Approximation Register (Sar)  Threshold Crossing Detector  Time Residue Generator (Trg)  Time-domain Adc  Time-to-digital Converter (Tdc)  Two-step Tdc  Voltage-to-time Converter (Vtc)  
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
Xing D., Zhu Y., Chan C.-H., Maloberti F., Seng-Pan U., Martins R.P.. Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(2), 489-501.
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.; et al.
Favorite | TC[WOS]:2 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2019/02/11
Reference Interference  Sar Adc  Time-interleaved Scheme  Two-step Sar Conversion  
Nano-Watt Class Energy-Efficient Capacitive Sensor Interface with On-Chip Temperature Drift Compensation Journal article
Tan-Tan Zhang, Man-Kay Law, Pui-In Mak, Mang-I Vai, Rui P. Martins. Nano-Watt Class Energy-Efficient Capacitive Sensor Interface with On-Chip Temperature Drift Compensation[J]. IEEE Sensors Journal, 2018, 18(7), 2870-2882.
Authors:  Tan-Tan Zhang;  Man-Kay Law;  Pui-In Mak;  Mang-I Vai;  Rui P. Martins
Favorite | TC[WOS]:17 TC[Scopus]:19 | Submit date：2019/02/11
Capacitive Sensor Interface  Energy Efficiency  High Accuracy  Mismatch Errors  Pressure Sensor  Temperature Compensation  Two-step Incremental-adc  Ultra-low Power  
A 310 nW 14.2-bit iterative-incremental ADC for wearable sensing systems Conference paper
Tan-Tan Zhang, Man-Kay Law, Bo Wang, Pui-In Mak, Mang-I Vai, Rui P. Martins. A 310 nW 14.2-bit iterative-incremental ADC for wearable sensing systems[C], 2018, 1-4.
Authors:  Tan-Tan Zhang;  Man-Kay Law;  Bo Wang;  Pui-In Mak;  Mang-I Vai; et al.
Favorite | TC[WOS]:3 TC[Scopus]:1 | Submit date：2019/02/11
Chopping  Dynamic Element Matching  Energy Efficiency  Incremental Adc  Sensor Interface  Two-step  Ultra-low-power  Vearable Sensing System  
A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC Journal article
Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC[J]. IEEE Journal of Solid-State Circuits, 2013, 48(8), 1783-1794.
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:27 TC[Scopus]:35  IF:4.6/5.6 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Sar Adc  Time-interleaved  Two-step Adc  
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC Conference paper
Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, R. P. Martins. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC[C], 2012.
Authors:  Si-Seng Wong;  U-Fat Chio;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:0 TC[Scopus]:10 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Binary-search Adc  Time-interleaved  Sar Adc  Two-step Adc