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Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs Conference paper
Guo Mingqiang, Sin Sai-Weng, Rui P. Martins. Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs[C]:IEEE, 2021, 248 - 249.
Authors:  Guo Mingqiang;  Sin Sai-Weng;  Rui P. Martins
Adobe PDF | Favorite | TC[WOS]:0 TC[Scopus]:2 | Submit date：2022/05/13
Adc  Background Calbration  Mismatch Calibration  Time-interleaved Converter  Timing Mismatch  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
Jiang, Dongyang, Qi, Liang, Sin, Sai Weng, Maloberti, Franco, Martins, Rui P.. A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56(8), 2375-2387.
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:14  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler Journal article
Jiang,Wenning, Zhu,Yan, Chan,Chi Hang, Murmann,Boris, Martins,Rui Paulo. A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 68(2), 557-568.
Authors:  Jiang,Wenning;  Zhu,Yan;  Chan,Chi Hang;  Murmann,Boris;  Martins,Rui Paulo
Favorite | TC[WOS]:25 TC[Scopus]:33  IF:5.2/4.5 | Submit date：2021/03/04
Analog-to-digital Converter  Sar Adc  Time-interleaved Adc  Current Integrating Sampler  Background Timing Skew Calibration  Timing Skew  
A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications Journal article
Guo,Mingqiang, Mao,Jiaji, Sin,Sai Weng, Wei,Hegong, Martins,Rui P.. A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications[J]. IEEE Access, 2020, 8, 138944-138954.
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Adobe PDF | Favorite | TC[WOS]:17 TC[Scopus]:22  IF:3.4/3.7 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Digital Background Calibration  Digital-mixing  Time-interleaved (Ti) Adc  Timing Mismatch  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
Guo,Mingqiang, Mao,Jiaji, Sin,Sai Weng, Wei,Hegong, Martins,Rui P.. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits, 2020, 55(3), 693-705.
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Adobe PDF | Favorite | TC[WOS]:51 TC[Scopus]:54  IF:4.6/5.6 | Submit date：2021/03/04
Analog-to-digital Converter (Adc)  Digital Background Calibration  Split Adc  Time-interleaved (Ti) Adc  Timing-skew Mismatch  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration Journal article
Guo Mingqiang, Mao Jiaji, Sin Sai-Weng, Wei Hegong, Rui P. Martins. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits, 2020, 55(3), 693-705.
Authors:  Guo Mingqiang;  Mao Jiaji;  Sin Sai-Weng;  Wei Hegong;  Rui P. Martins
Adobe PDF | Favorite | TC[WOS]:51 TC[Scopus]:54  IF:4.6/5.6 | Submit date：2022/08/20
Analog-to-Digital Converter (Adc), Digital Background CalibraTion, Split Adc, Time-interleaved (Ti) Adc, Timing-skew Mismatch  
A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Guo, M., Mao, J., Sin, S. W., Wei, H., Martins, R. P.. A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration[C], 2019.
Authors:  Guo, M.;  Mao, J.;  Sin, S. W.;  Wei, H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
SAR analog-to-digital converter (ADC)  time-interleaved (TI) ADC  timing-skew calibration  split ADC  background mismatch calibration  
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Guo,Mingqiang, Mao,Jiaji, Sin,Sai Weng, Wei,Hegong, Martins,R. P.. A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2019, 8780222.
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
Adobe PDF | Favorite | TC[WOS]:13 TC[Scopus]:9 | Submit date：2021/03/09
Sar Analog-to-digital Converter (Adc)  Time-interleaved (Ti) Adc  Timing-skew Calibration  Split Adc  Background Mismatch Calibration  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
Liu J., Chan C.-H., Sin S.-W., Seng-Pan U., Martins R.P.. Accuracy-enhanced variance-based time-skew calibration using SAR as window detector[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(2), 481-485.
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:2.8/2.8 | Submit date：2019/02/13
Bandwidth Mismatches  Split-digital To Analog Converter (Dac)  Successive-approximation-register (Sar) Analog-to-digital Converter (Adc)  Time-interleaved (Ti)  Variance Based  Window Detector (Wd)  
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS Journal article
Wang, X. Shawn, Jin, Xin, Du, Jieqiong, Li, Yilei, Du, Yuan, Wong, Chien-Heng, Kuan, Yen-Cheng, Chan, Chi-Hang, Chang, Mau-Chung Frank. A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65(11), 1534-1538.
Authors:  Wang, X. Shawn;  Jin, Xin;  Du, Jieqiong;  Li, Yilei;  Du, Yuan; et al.
Favorite | TC[WOS]:4 TC[Scopus]:6  IF:4.0/3.7 | Submit date：2019/01/17
Analog-to-digital Converter (Adc)  Virtual-ground Sampling  Sar  Time-interleaved