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A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer with Integrated Transformer-Based Gate Inductor and IM2 Injection Technique Journal article
Vitee,Nandini, Ramiah,Harikrishnan, Mak,Pui In, Yin,Jun, Martins,Rui P.. A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer with Integrated Transformer-Based Gate Inductor and IM2 Injection Technique[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, 28(3), 700-713.
Authors:  Vitee,Nandini;  Ramiah,Harikrishnan;  Mak,Pui In;  Yin,Jun;  Martins,Rui P.
Favorite | TC[WOS]:15 TC[Scopus]:25  IF:2.8/2.8 | Submit date：2021/03/04
Balun-low-noise Amplifier (Lna) Mixer  Cmos  High Linearity  Inductively Source Degeneration Transconductor  Low-power  Second-order Intermodulation (Im2) Injection  Third-order Input Intercept Point (Iip3)  Volterra Series  
A 0.096-mm2 1-20-GHz triple-path noise- canceling common-gate common-source LNA with dual complementary pMOS-nMOS configuration Journal article
Yu,Haohong, Chen,Yong, Boon,Chirn Chye, Mak,Pui In, Martins,Rui P.. A 0.096-mm2 1-20-GHz triple-path noise- canceling common-gate common-source LNA with dual complementary pMOS-nMOS configuration[J]. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2019, 68(1), 144-159.
Authors:  Yu,Haohong;  Chen,Yong;  Boon,Chirn Chye;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:67 TC[Scopus]:75  IF:4.1/4.2 | Submit date：2021/03/09
Cmos  Common Gate (Cg)  Common Source (Cs)  Input Third-order Intercept Point (Iip3)  Noise Figure (Nf)  Partial Distortion Canceling  Pmos-nmos Configuration  Resistive Feedback  Triple-path And Dual-path Noise CaNceling (Nc)  Wideband Input Matching  Wideband Low-noise Amplifier (Lna)  
A 0.096-mm2 1-to-20-GHz Triple-Path Noise-Cancelling Common-Gate Common-Source LNA with Complementary pMOS-nMOS Configuration Journal article
Yu, H., Chen, Y., Boon, C., Mak, P. I., Martins, R. P.. A 0.096-mm2 1-to-20-GHz Triple-Path Noise-Cancelling Common-Gate Common-Source LNA with Complementary pMOS-nMOS Configuration[J]. IEEE Transactions on Microwave Theory and Techniques, 2019, 144-159.
Authors:  Yu, H.;  Chen, Y.;  Boon, C.;  Mak, P. I.;  Martins, R. P.
Favorite | TC[WOS]:67 TC[Scopus]:75 | Submit date：2022/01/25
Cmos  Common Gate (Cg)  Common Source (Cs)  Input Third-order Intercept Point (Iip3)  Noise Figure (Nf)  Partial Distortion Canceling  Pmos–nmos Configuration  Resistive Feedback  Triple-path And Dual-path Noise CaNceling (Nc)  Wideband Input Matching  Wideband Low-noise Amplifier (Lna)