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A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC Journal article
Zhong, Jianyu, Zhu, Yan, Chan, Chi-Hang, Sin, Sai-Weng, U, Seng-Pan, Martins, Rui Paulo. A 12b 180MS/s 0.068mm(2) With Full-Calibration-Integrated Pipelined-SAR ADC[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64(7), 1684-1695.
Authors:  Zhong, Jianyu;  Zhu, Yan;  Chan, Chi-Hang;  Sin, Sai-Weng;  U, Seng-Pan; et al.
Favorite | TC[WOS]:23 TC[Scopus]:30  IF:5.2/4.5 | Submit date：2018/10/30
Analog-to-digital Converter (Adc)  Successive Approximation Architecture  Low Power  Switched-capacitor Circuits  
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC Journal article
Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Wng Sin, Seng-Pan U, Rui Paulo Martins. A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, 64(7), 1684-1695.
Authors:  Jianyu Zhong;  Yan Zhu;  Chi-Hang Chan;  Sai-Wng Sin;  Seng-Pan U; et al.
Favorite | TC[WOS]:23 TC[Scopus]:30 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Low Power  Successive Approximation Architecture  Switched-capacitor Circuits  
16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
Chan, C. H., Zhu, Y., Ho, I.M., Zhang, W.H., Martins, R. P.. 16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration[C], 2017.
Authors:  Chan, C. H.;  Zhu, Y.;   Ho, I.M.;  Zhang, W.H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
—Analog-to-digital converter (ADC)  successive approximation architecture  low power  switched-capacitor circuits.