×
验证码:
换一张
Forgotten Password?
Stay signed in
Login With UMPASS
English
|
繁體
Login With UMPASS
Log In
ALL
ORCID
TI
AU
PY
SU
KW
TY
JN
DA
IN
PB
FP
ST
SM
Study Hall
Image search
Paste the image URL
Home
Faculties & Institutes
Scholars
Publications
Subjects
Statistics
News
Search in the results
Faculties & Institutes
THE STATE KEY LA... [1]
INSTITUTE OF MIC... [1]
Authors
RUI PAULO DA SIL... [1]
LU YAN [1]
Document Type
Conference paper [1]
Journal article [1]
Date Issued
2022 [1]
2020 [1]
Language
英語English [2]
Source Publication
2020 IEEE Intern... [1]
IEEE Journal of ... [1]
Indexed By
SCIE [1]
Funding Organization
Funding Project
×
Knowledge Map
UM
Start a Submission
Submissions
Unclaimed
Claimed
Attach Fulltext
Bookmarks
Browse/Search Results:
1-2 of 2
Help
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Submit date Ascending
Submit date Descending
Issue Date Ascending
Issue Date Descending
Author Ascending
Author Descending
Title Ascending
Title Descending
Journal Impact Factor Ascending
Journal Impact Factor Descending
WOS Cited Times Ascending
WOS Cited Times Descending
A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless Fast Charging
Journal article
Mao, Fangyu, Lu, Yan, Martins, Rui P.. A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless Fast Charging[J]. IEEE Journal of Solid-State Circuits, 2022, 57(6), 1888-1898.
Authors:
Mao, Fangyu
;
Lu, Yan
;
Martins, Rui P.
Favorite
|
TC[WOS]:
2
TC[Scopus]:
4
IF:
4.6
/
5.6
|
Submit date:2022/05/17
Device-to-device (D2d) Wireless Charging
Gallium-nitride (Gan)
Reconfigurable Controller
Single-stage Structure
Step-down Rectifier (Sdr)
Step-up Power Amplifier (Supa)
Zero-voltage Switching (Zvs)
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration
Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:
Song, Y.
;
Zhu, Y.
;
Chan, C. H.
;
Martins, R. P.
Favorite
|
|
Submit date:2022/01/25
analogue-digital conversion
calibration
CMOS digital integrated circuits
digital-analogue conversion
low-power electronics
preamplifiers
background inter-stage offset calibration
noise-shaping SAR hybrid architecture
NS-SAR
SNDR
power-hungry preamplifiers
low-noise targets
Schreier FoM
0-1 MASH SDM
pipeline-SAR structure
single-channel ADC
power-hungry residue amplifier
ADC power
area-hungry bit weight calibration
dynamic amplifier
pipeline operation
power efficiency
partial interleaving structu