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A 27 W Wireless Power Transceiver With Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control Journal article
Ma, Xiaofei, Ki, Wing Hung, Lu, Yan. A 27 W Wireless Power Transceiver With Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control[J]. IEEE Journal of Solid-State Circuits, 2024, 59(6), 1782-1793.
Authors:  Ma, Xiaofei;  Ki, Wing Hung;  Lu, Yan
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/07/04
Ac-dc  Adaptive Dead Time  Dc-ac  Device-to-device (D2d)  Gan Driver  Power Amplifier (Pa)  Rectifier  Single-stage Regulation  Wireless Fast Charging  Wireless Power Transfer  Zero-voltage Switching (Zvs)  
A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless Fast Charging Journal article
Mao, Fangyu, Lu, Yan, Martins, Rui P.. A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless Fast Charging[J]. IEEE Journal of Solid-State Circuits, 2022, 57(6), 1888-1898.
Authors:  Mao, Fangyu;  Lu, Yan;  Martins, Rui P.
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:4.6/5.6 | Submit date：2022/05/17
Device-to-device (D2d) Wireless Charging  Gallium-nitride (Gan)  Reconfigurable Controller  Single-stage Structure  Step-down Rectifier (Sdr)  Step-up Power Amplifier (Supa)  Zero-voltage Switching (Zvs)  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier with Enhancements of DC Gain, GBW and Slew Rate Journal article
Zushu Yan, Pui-In Mak, Man-Kay Law, Rui P. Martins, Franco Maloberti. Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier with Enhancements of DC Gain, GBW and Slew Rate[J]. IEEE Journal of Solid-State Circuits, 2015, 50(10), 2353-2366.
Authors:  Zushu Yan;  Pui-In Mak;  Man-Kay Law;  Rui P. Martins;  Franco Maloberti
Favorite | TC[WOS]:61 TC[Scopus]:67 | Submit date：2019/02/11
Area Efficiency  Cmos  Current Mirror  Dc Gain  Differential-pair (Dp) Amplifier  Frequency Compensation  Gain-bandwidth Product (Gbw)  Low Temperature Polysilicon Lcd  Multi-stage Amplifier  Nested Current Mirror  Rail-to-rail Output Swing  Single-stage Amplifier  Slew Rate (Sr)  Stability