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A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors Conference paper
Zhang, Minglei, Cao, Yuefeng, Zhu, Yan, Chan, Chi-Hang, Martins, R. P.. A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors[C]:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Zhang, Minglei;  Cao, Yuefeng;  Zhu, Yan;  Chan, Chi-Hang;  Martins, R. P.
Favorite | TC[Scopus]:2 | Submit date：2023/07/12
Dynamic Amplifier  Residue Amplifier  Pipelined-sar Adc  Linearization Technique  Bypass Capacitor  
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
Zheng, Z., Wei, W., Lagos, J., Martens, E., Zhu, Y., Chan, C. H., Craninckx, J., Martins, R. P.. 16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation[C], 2020.
Authors:  Zheng, Z.;  Wei, W.;  Lagos, J.;  Martens, E.;  Zhu, Y.; et al.
Favorite |  | Submit date：2022/01/25
Amplifiers  Analogue-digital Conversion  Calibration  Interpolation  Dynamic Pipelined Adc  Dynamic Pipelined Architecture  Linearized Dynamic Amplifier  Post-amplification Residue Generation Scheme  Residue Amplification  Complex Residue-transferring Realization  Residue Amplifier  Power Consumption  Sar Adc  Calibration Complexity  Aggressive Interpolation Factor  Flash Adc  Mm-wave 5g Receivers  Adc-based Serial Links  Power 5.5 Mw  Calibration  Quantization (Signal)  Clocks  System-on-chip  Interpolation  Prototype  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  ; et al.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC with Dynamic Gm-R-Based Amplifier Journal article
Jiang,Wenning, Zhu,Yan, Zhang,Minglei, Chan,Chi Hang, Martins,Rui Paulo. A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC with Dynamic Gm-R-Based Amplifier[J]. IEEE Journal of Solid-State Circuits, 2020, 55(2), 322-332.
Authors:  Jiang,Wenning;  Zhu,Yan;  Zhang,Minglei;  Chan,Chi Hang;  Martins,Rui Paulo
Favorite | TC[WOS]:42 TC[Scopus]:51  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Gm-r Amplifier  Pipelined-successive Approximation Register (Sar) Adc  Residue Amplifier (Ra)  Sar  Sar-assisted Pipelined Adc  Temperature Compensation