English | 繁體

Search in the results

UM

Browse/Search Results:  1-3 of 3 Help

Selected(0)Clear Items/Page:    Sort:
A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE Conference paper
Zhang, Zhaoyu, Zhang, Zhao, Chen, Yong, Wang, Guoqing, Shen, Xinyu, Qi, Nan, Li, Guike, Yu, Shuangming, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE[C], New York, USA:IEEE, 2023, 177-180.
Authors:  Zhang, Zhaoyu;  Zhang, Zhao;  Chen, Yong;  Wang, Guoqing;  Shen, Xinyu; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/02/22
Charge Sharing Integrator  Clock And Data Recovery (Cdr)  Cmos  Continuous-rate  Reference-less  
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS Journal article
Xiaoteng Zhao, Yong Chen, Lin Wang, Pui In Mak, Franco Maloberti, Rui P. Martins. A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2022, 57(5), 1358-1371.
Authors:  Xiaoteng Zhao;  Yong Chen;  Lin Wang;  Pui In Mak;  Franco Maloberti; et al.
Favorite | TC[WOS]:10 TC[Scopus]:14  IF:4.6/5.6 | Submit date：2022/05/13
And Zero Net Current (Znc)  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Cmos  Four-level Pulse-amplitude Modulation (Pam)  Frequency Detector (Fd)  Half-rate  Negative Net Current (Nnc)  Positive Net Current (Pnc)  Reference-less  
A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS Conference paper
Zhao, Xiaoteng, Chen, Yong, Wang, Lin, Mak, Pui In, Maloberti, Franco, Martins, Rui P.. A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS[C], 2021, 131-134.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Wang, Lin;  Mak, Pui In;  Maloberti, Franco; et al.
Favorite | TC[WOS]:6 TC[Scopus]:9 | Submit date：2021/09/20
4-level Pulse Amplitude Modulation (Pam-4)  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Cmos  Frequency Detector (Fd)  Half-rate  Negative (Nnc) Net Current  Positive (Pnc)  Reference Less  Single Loop  Zero (Znc)