×
验证码:
换一张
Forgotten Password?
Stay signed in
Login With UMPASS
English
|
繁體
Login With UMPASS
Log In
ALL
ORCID
TI
AU
PY
SU
KW
TY
JN
DA
IN
PB
FP
ST
SM
Study Hall
Image search
Paste the image URL
Home
Faculties & Institutes
Scholars
Publications
Subjects
Statistics
News
Search in the results
Faculties & Institutes
INSTITUTE OF MIC... [3]
Faculty of Scien... [3]
THE STATE KEY LA... [2]
Authors
MAK PUI IN [3]
CHEN YONG [2]
RUI PAULO DA SIL... [1]
YIN JUN [1]
Document Type
Journal article [3]
Date Issued
2024 [1]
2021 [1]
2020 [1]
Language
英語English [3]
Source Publication
IEEE Journal of ... [1]
IEEE Solid-State... [1]
IEEE Transaction... [1]
Indexed By
SCIE [2]
ESCI [1]
Funding Organization
Funding Project
×
Knowledge Map
UM
Start a Submission
Submissions
Unclaimed
Claimed
Attach Fulltext
Bookmarks
Browse/Search Results:
1-3 of 3
Help
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Issue Date Ascending
Issue Date Descending
Journal Impact Factor Ascending
Journal Impact Factor Descending
WOS Cited Times Ascending
WOS Cited Times Descending
Submit date Ascending
Submit date Descending
Title Ascending
Title Descending
Author Ascending
Author Descending
A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment
Journal article
Li, Haoran, Xu, Tailong, Meng, Xi, Yin, Jun, Martins, Rui P., Mak, Pui In. A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:
Li, Haoran
;
Xu, Tailong
;
Meng, Xi
;
Yin, Jun
;
Martins, Rui P.
; et al.
Favorite
|
TC[WOS]:
0
TC[Scopus]:
0
IF:
4.6
/
5.6
|
Submit date:2024/10/10
Fast Locking
Frequency Synthesis
Frequency-locked Loop (Fll)
Low Jitter
Millimeter-wave (Mm-wave)
Phase-locked Loop (Pll)
Reference (Ref.) Spur
Sub-sampling Phase Detector (Sspd)
Voltage-controlled Oscillator (Vco)
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM
Journal article
Yang, Zunsong, Chen, Yong, Yuan, Jia, Mak, Pui In, Martins, Rui P.. A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 30(2), 238-242.
Authors:
Yang, Zunsong
;
Chen, Yong
;
Yuan, Jia
;
Mak, Pui In
;
Martins, Rui P.
Favorite
|
TC[WOS]:
20
TC[Scopus]:
21
IF:
2.8
/
2.8
|
Submit date:2022/03/04
Binary Frequency Shift Keying (Bfsk)
Frequency-locked Loop (Fll)
Integer-n
Phase Detector (Pd)
Phase Noise (Pn)
Phase-locked Loop (Pll)
Push-pull
Reference (Ref) Spur
Sub-sampling (Ss)
Voltage-controlled Oscillator (Vco)
A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM
Journal article
Yang,Zunsong, Chen,Yong, Mak,Pui In, Martins,Rui P.. A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM[J]. IEEE Solid-State Circuits Letters, 2020, 3, 494-497.
Authors:
Yang,Zunsong
;
Chen,Yong
;
Mak,Pui In
;
Martins,Rui P.
Favorite
|
TC[WOS]:
18
TC[Scopus]:
19
|
Submit date:2021/03/09
Cmos
In-band Phase Noise (Pn)
Narrow-pulse-sampling (Nps)
Phase-locked Loop (Pll)
Reference (Ref) Spur
T-shape Switch
Type-i
Voltage-controlled Oscillator (Vco)