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A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
A 21.8-41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller Journal article
Chen, Wen, Shu, Yiyang, Yin, Jun, Mak, Pui In, Gao, Xiang, Luo, Xun. A 21.8-41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller[J]. IEEE Transactions on Microwave Theory and Techniques, 2024.
Authors:  Chen, Wen;  Shu, Yiyang;  Yin, Jun;  Mak, Pui In;  Gao, Xiang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.1/4.2 | Submit date：2024/05/16
Detectors  Fast Locking  Frequency Locked Loops  Jitter  Jitter  Millimeter Wave (mm-Wave)  Phase Locked Loops  Phase Noise  Subsampling Phase-locked Loop (Sspll)  Voltage-controlled Oscillators  Wideband  Wideband  
A −246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT Conference paper
Yang, X., Chan, C. H., Zhu, Y., Martins, R. P.. A −246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT[C], 2019.
Authors:  Yang, X.;  Chan, C. H.;  Zhu, Y.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
Phase locked loops  Jitter  Clocks  Phase noise  Wideband  Frequency locked loops  
Transformer-Based Design Techniques for Oscillators and Frequency Dividers Book
Howard Cam Luong, Jun Yin. Transformer-Based Design Techniques for Oscillators and Frequency Dividers[M]. Switzerland:Springer, 2016.
Authors:  Howard Cam Luong;  Jun Yin
Favorite | TC[Scopus]:23 | Submit date：2019/04/03
Cmos Pll Synthesizers  Voltage-controlled Oscillators  Mm-wave Integrated Circuits And Systems  Cmos Radio-frequency Integrated Circuits  Integrated Frequency Synthesizers For Wireless Systems  Low Power Vco Design  Low-voltage Cmos Rf Frequency  Oscillators And Frequency Dividers  Phase-locked Loops  Synthesizers  
Two-step channel selection technique by programmable digital-double quadrature sampling for complex low-IF receivers Journal article
Pui-In Mak, Seng-Pan U, R.P. Martins. Two-step channel selection technique by programmable digital-double quadrature sampling for complex low-IF receivers[J]. Electronics Letters, 2003, 39(11), 825-827.
Authors:  Pui-In Mak;  Seng-Pan U;  R.P. Martins
Favorite | TC[WOS]:5 TC[Scopus]:4 | Submit date：2019/02/11
Channel Allocation  Digital Phase Locked Loops  Phase Noise  Frequency Synthesizers  
A chaotic masking system of network traffic Conference paper
Li M., Jia W., Zhao W.. A chaotic masking system of network traffic[C], 2001, 310-315.
Authors:  Li M.;  Jia W.;  Zhao W.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/11
Chaos  Network Traffic  Phase-locked Loops  Secure Network Communications  Traffic Masking