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A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations Journal article
Zhu, Yan, Chan, Chi-Hang, Pan, Seng U., Martins, Rui Paulo. A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25(1), 354-363.
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Pan, Seng U.;  Martins, Rui Paulo
Favorite | TC[WOS]:11 TC[Scopus]:14  IF:2.8/2.8 | Submit date：2018/10/30
Offset Calibration  Partial Interleaving (Pi)  Pipelined-sar  Stage-gain Error Calibration