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An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
Zhang, Hongshuai, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57(5), 1480-1491.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite | TC[WOS]:8 TC[Scopus]:10  IF:4.6/5.6 | Submit date：2022/05/13
Amplifier Linearity Enhancement  Analog-to-digital Converter (Adc)  Background Offset Calibration  Digital Reconstruction Filter  Dwa  Energy And Area Efficient  Inherent Gain Error Tolerant  Inter-stage Gain Error  Noise Shaping (Ns)  Oversampling  Partial Interleaving  Pipelined Successive Approximation (Sar)  Quantization Leakage Error  
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC Journal article
Song,Yan, Zhu,Yan, Chan,Chi Hang, Martins,Rui P.. A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC[J]. IEEE Journal of Solid-State Circuits, 2021, 56(6), 1772-1783.
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite | TC[WOS]:14 TC[Scopus]:17  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Noise-shaping (Ns)  Offset Calibration  Successive Approximation Register (Sar)-assisted Pipeline  Time Interleaving  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
Background Offset Calibration for Comparator Based on Temperature Drift Profile Journal article
Li,Xiaochao, Chan,Chi Hang, Zhang,Qi, Zhu,Yan, Martins,R. P.. Background Offset Calibration for Comparator Based on Temperature Drift Profile[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66(10), 1648-1652.
Authors:  Li,Xiaochao;  Chan,Chi Hang;  Zhang,Qi;  Zhu,Yan;  Martins,R. P.
Favorite | TC[WOS]:4 TC[Scopus]:7  IF:4.0/3.7 | Submit date：2021/03/09
Background Self-calibration  Offset Drift  Preamplifier Comparator  
Low-Offset and Low-Noise Comparators with Calibration Techniques Thesis
Zhang, W.H., Zhu, Y., Chan, C. H.. Low-Offset and Low-Noise Comparators with Calibration Techniques[D], 2018.
Authors:  Zhang, W.H.;  Zhu, Y.;  Chan, C. H.
Favorite |  | Submit date：2023/08/31
Low-Noise Comparators  Offset Calibration Techniques  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
Chan, Chi-Hang, Zhu, Yan, Zhang, Wai-Hong, Seng-Pan, U., Martins, Rui Paulo. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53(3), 850-860.
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | TC[WOS]:60 TC[Scopus]:66  IF:4.6/5.6 | Submit date：2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
16.4 A 5mW 7b 2.4 GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
Chan, C. H., Zhu, Y., Ho, I. M., Zhang, W. H., U, S. P., Martins, R. P.. 16.4 A 5mW 7b 2.4 GS/s 1-then-2b/cycle SAR ADC with background offset calibration[C], 2017.
Authors:  Chan, C. H.;  Zhu, Y.;  Ho, I. M.;  Zhang, W. H.;  U, S. P.; et al.
Favorite |  | Submit date：2022/01/25
SAR ADC  Offset Calibration  
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations Journal article
Zhu, Yan, Chan, Chi-Hang, Pan, Seng U., Martins, Rui Paulo. A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25(1), 354-363.
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Pan, Seng U.;  Martins, Rui Paulo
Favorite | TC[WOS]:11 TC[Scopus]:14  IF:2.8/2.8 | Submit date：2018/10/30
Offset Calibration  Partial Interleaving (Pi)  Pipelined-sar  Stage-gain Error Calibration  
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS Journal article
Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins. An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2016, 51(5), 1223-1234.
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  Rui Paulo Martins
Favorite | TC[WOS]:29 TC[Scopus]:33 | Submit date：2019/02/11
Offset Calibration  Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Sar Logic  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan (Ben) U, Rui Paulo Martins. A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC[J]. IEEE Journal of Solid-State Circuits, 2016, 51(2), 365-377.
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite | TC[WOS]:32 TC[Scopus]:37 | Submit date：2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration