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A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing Journal article
Qi, L., Sin, W., U, S.P., Maloberti, F., Martins, R. P.. A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing[J]. IEEE Transactions on Circuits and Systems I - Regular Papers, 2017, 2641-2654.
Authors:  Qi, L.;  Sin, W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/24
Analog-to-digital Converter (Adc)  Discrete-time (Dt) Delta Sigma (Δς) Modulator  Multi-stage Noise Shaping (Mash)  Wideband  Power-efficient  Opamp Sharing  Multirate  Sar Quantizer  
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing Journal article
Liang Qi, Sai-Weng Sin, Seng-Pan, U., Franco Maloberti, Rui Paulo Martins. A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64(10), 2641-2654.
Authors:  Liang Qi;  Sai-Weng Sin;  Seng-Pan, U.;  Franco Maloberti;  Rui Paulo Martins
Favorite | TC[WOS]:35 TC[Scopus]:44  IF:5.2/4.5 | Submit date：2018/10/30
Analog-to-digital Converter (Adc)  Discrete-time (Dt) Delta Sigma (Delta Sigma) Modulator  Multi-stage Noise Shaping (Mash)  Wideband  Power-efficient  Opamp Sharing  Multirate  Successive Approximation Register (Sar) Quantizer  
Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering Book
U Seng Pan, Martins Rui Paulo, Epifanio da Franca Jose de Albuquerque. Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering[M]. US:Springer US, 2006, 250.
Authors:  U Seng Pan;  Martins Rui Paulo;  Epifanio da Franca Jose de Albuquerque
Favorite | TC[Scopus]:0 | Submit date：2019/02/26
Cmos  Cmos Analog Integrated Circuit  Filter  Front-end Filtering  Gain & Offset Compensation  High-frequency  Multirate Signal Processing  Secs  Switched-capacitor  The Kluwer International Series In engIneerIng And Computer  Timing-mismatch And Jitter  Calculus  Consumption  Integrated Circuit  
A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μm CMOS Journal article
U S.-P., Martins R.P., Franca J.E.. A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μm CMOS[J]. IEEE Journal of Solid-State Circuits, 2004, 39(1), 87-99.
Authors:  U S.-P.;  Martins R.P.;  Franca J.E.
Favorite | TC[WOS]:2 TC[Scopus]:16  IF:4.6/5.6 | Submit date：2019/02/11
Autozeroing  Bandpass  Cmos Analog Integrated Circuits  Direct-digital Synthesis  Filters  Frequency-translated Filtering  Interpolation  Multirate Signal Processing  Sampled Data Circuits  Signal Sampling/reconstruction  Switched-capacitor Filters