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A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC Journal article
Zhao, Hongzhi, Zhang, Minglei, Zhu,Yan, Martins, R. P., Chan,Chi Hang. A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3586-3597.
Authors:  Zhao, Hongzhi;  Zhang, Minglei;  Zhu,Yan;  Martins, R. P.;  Chan,Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2023/08/29
Analog-to-digital Converter (Adc)  Multi-bit/cycle Successive-approximation Register (Sar) Adc  Time-domain Quantization  Voltage-to-time (V2t) Buffer  Linearization  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
Chan, Chi-Hang, Zhu, Yan, Zhang, Wai-Hong, Seng-Pan, U., Martins, Rui Paulo. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53(3), 850-860.
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | TC[WOS]:60 TC[Scopus]:66  IF:4.6/5.6 | Submit date：2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving