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A 16-MHz Crystal Oscillator With 17.5-μs Start-Up Time Under 104-ppm-ΔF Injection Using Automatic Phase-Error Correction Journal article
Wang, Zixuan, Wang, Xin, Lei, Ka Meng, Zhang, Wenjing, Yin, Yunjin, Xu, Tailong, Cai, Zhikuang, Guo, Yufeng, Mak, Pui-In. A 16-MHz Crystal Oscillator With 17.5-μs Start-Up Time Under 104-ppm-ΔF Injection Using Automatic Phase-Error Correction[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024, 59(11), 3780-3790.
Authors:  Wang, Zixuan;  Wang, Xin;  Lei, Ka Meng;  Zhang, Wenjing;  Yin, Yunjin; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/05/16
Automatic Phase-error Correction (Apec)  Crystal Oscillator (Xo)  Fast Start-up  Injection-frequency-mismatch Tolerance  Single-ended Energy Injection  
A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 2019, 1161-1172.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |   IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter  Iadc  Incremental Adc  Sigma-delta  Linear  Exponential  Accumulation  Two-phase  Multi-bit  Mismatch Error  Dynamic Element Matching (Dem)  Data Weighting Average (Dwa)  High Linearity  Notch  
A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
Wang, B., Sin,Sai Weng, Seng-Pan,S. P.U., Maloberti,Franco, Martins,Rui P.. A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2019, 54(4), 1161-1172.
Authors:  Wang, B.;  Sin,Sai Weng;  Seng-Pan,S. P.U.;  Maloberti,Franco;  Martins,Rui P.
Favorite | TC[WOS]:44 TC[Scopus]:55  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Data Weighting Average  Dynamic Element Matching (Dem)  High Linearity  Incremental Adc (iAdc)  Linear-exponential Accumulation  Mismatch Error  Multi-bit  Notch  Sigma Delta  Two Phase  
A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement Journal article
Yu, Wei-Han, Peng, Xingqiang, Mak, Pui-In, Martins, Rui P.. A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64(11), 2844-2857.
Authors:  Yu, Wei-Han;  Peng, Xingqiang;  Mak, Pui-In;  Martins, Rui P.
Favorite | TC[WOS]:5 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2018/10/30
Aa Battery  Antenna Impedance Mismatch  Class-d  Cmos  Digital Am Modulation  Dynamic Matching Network (Dmn)  Error-vector Magnitude (Evm)  Inverter Chain  Leakage Current  Matching Network (Mn)  Polar  Power Amplifier (Pa)  Power-added Efficiency (Pae)  Power Gating  
An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs Conference paper
Li D., Sin S.-W., Seng-Pan U., Martins R.P.. An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs[C], 2010, 208-211.
Authors:  Li D.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | TC[WOS]:2 TC[Scopus]:3 | Submit date：2019/02/11
Capacitor Mismatch  Digital Calibration  Interstage Gain Error  Pipelined Adcs